Intel Corporation

Quat T Vu

Qing Ma

Alan M Myers

R Scott List

Sarah E Kim

James G Maveety

Jian Li

Steven N Towle

Xiao-Chun Mu

Brian S Doyle

Chun Mu

Donald S Gardner

Larry E Mosley

David B Fraser

Ravi S Prasher

Ravi V Mahajan

Jin Hyung Lee

Gilroy J Vandentop

Maria V Henao

Ian A Young

Ravindranath Vithal Mahajan

Chien Chiang

Yuegang Zhang

Brian E Roberds

Thomas N Marieb

Eng T Gaw

Steve Towle

Martha Jones

Tuy T Ton

Sandy S Lee

Leopold Yau

Thomas N D Marieb

Ling-Chu Chien

Maria Henao

Trenches may be formed in the upper surfaces of a pair of wafers. Each trench may be coated with a catalyst that is capable of removing oxygen or hydrogen from a fluid used for cooling in a system making use of the electroosmotic effect for pumping. Channels may be formed to communicate fluid to and from the trench coated with the catalyst. The substrates may be combined in face-to-face abutment, for example using copper-to-copper bonding to form a re-combiner.

Integrated re-combiner for electroosmotic pumps using porous frits

A stack of heat generating integrated circuit chips may be provided with intervening cooling integrated circuit chips. The cooling integrated circuit chips may include microchannels for the flow of the cooling fluid. The cooling fluid may be pumped using the integrated electroosmotic pumps. Removal of cooling fluid gases may be accomplished using integrated re-combiners in some embodiments.

Method of forming a stack of heat generating integrated circuit chips with intervening cooling integrated circuit chips

An electroosmotic pump may be fabricated using semiconductor processing techniques with a nanoporous open cell dielectric frit. Such a frit may result in an electroosmotic pump with better pumping capabilities.

Electroosmotic pump using nanoporous dielectric frit

An integrated circuit to be cooled may be abutted in face-to-face abutment with a cooling integrated circuit. The cooling integrated circuit may include electroosmotic pumps to pump cooling fluid through the cooling integrated circuits via microchannels to thereby cool the heat generating integrated circuit. The electroosmotic pumps may be fluidically coupled to external radiators which extend upwardly away from a package including the integrated circuits. In particular, the external radiators may be mounted on tubes which extend the radiators away from the package.

Using external radiators with electroosmotic pumps for cooling integrated circuits

An integrated electroosmotic pump may be incorporated in the same integrated circuit package with a re-combiner, and an integrated circuit chip to be cooled by fluid pumped by the electroosmotic pump.

Packaged electroosmotic pumps using porous frits for cooling integrated circuits

A method of fabricating microelectronic dice by providing or forming a first encapsulated die assembly and a second encapsulated die assembly. Each of the encapsulated die assemblies includes at least one microelectronic die disposed in a packaging material. Each of the encapsulated die assemblies has an active surface and a back surface. The encapsulated die assemblies are attached together in a back surface-to-back surface arrangement. Build-up layers are then formed on the active surfaces of the first and second encapsulated assemblies, preferably, simultaneously. Thereafter, the microelectronic dice are singulated, if required, and the microelectronic dice of the first encapsulated die assembly are separated from the microelectronic dice of the second encapsulated die assembly.

Process for forming a direct build-up layer on an encapsulated die packages utilizing intermediate structures

In one embodiment, a capacitor comprises a substrate defining a first electrical terminal; a catalyst layer disposed on the substrate; a plurality of carbon nanotubes disposed on the catalyst layer; a dielectric layer disposed over the plurality of carbon nanotubes; and a conductive layer disposed on the dielectric layer and defining a second electrical terminal.

Capacitor with carbon nanotubes

Electroosmotic pumps using porous frits for cooling integrated circuit stacks

A microelectronic substrate including at least one microelectronic device disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic devices, or a plurality microelectronic devices encapsulated without the microelectronic substrate core. At least one conductive via extended through the substrate, which allows electrical communication between opposing sides of the substrate. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic device, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

Microelectronic substrates with integrated devices

Expanded bond pads are formed over a passivation layer on a semiconductor wafer before the wafer is diced into individual circuit chips. After dicing, the individual chips are packaged by fixing each chip within a package core and building up one or more metallization layers on the resulting assembly. In at least one embodiment, a high melting temperature (lead free) alternative bump metallurgy (ABM) form of controlled collapse chip connect (C4) processing is used to form relatively wide conducting platforms over the bond pads on the wafer.

Method for packaging a microelectronic device using on-die bond pad expansion

The present disclosure relates generally to microelectronic technology, and more specifically, to an apparatus used for the cooling of active electronic devices utilizing electro-osmotic pumps and micro-channels.

Electro-osmotic pumps and micro-channels

A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby

A microelectronic device includes a microelectronic die having an interfacial metal layer deposited over an active surface thereof to perform a signal distribution function within the device. The microelectronic die is fixed within a package core to form a die/core assembly. One or more metallization layers may then be built up over the die/core assembly as part of a packaging scheme. The interfacial metal layer can be applied either before or after the die is fixed within the package core. In one approach, the interfacial layer is applied during wafer-level processing.

Microelectronic device having signal distribution functionality on an interfacial layer thereof

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Santa Clara, CA, United States of America

Quat T Vu