Intel Corporation

Quan H Ngo

Daniel R Elmhurst

Robert Melcher

Karthikeyan Ramamurthi

Saad Monasa

An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

High bandwidth datapath load and test of multi-level memory cells

An interim density top boot flash memory architecture may be implemented by locking a portion or block of memory to prevent memory read and write accesses, thereby reducing the overall capacity of the memory. At the same time, this may be done without interfering with the access to parameters needed for implementing booting. In some embodiments, the locked memory may be placed at a block above the lowest addressable block that is accessed by an internal address.

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Sacramento, CA, United States of America

Quan H Ngo