United Microelectronics Corp.

Gigadevice Semiconductor (beijing) Inc.

Qingming Shu

Jiang Yi Liu

Jianjun Zhang

Hongyi Chen

Sai Zhang

Hong Hu

Ronghua Pan

An enhanced Flash chip of SPI interface and a method for packaging chip, to solve the problems of high design complexity, long design period and high design cost. The chip comprises SPI FLASH and RPMC which are packaged integrally; the SPI FLASH and the RPMC comprise an independent controller, respectively; the same IO pins in SPI FLASH and RPMC are mutually connected and are connected to the same external sharing pin of the chip. The SPI FLASH and the RPMC further comprise an internal IO pin, respectively, in which the internal IO pin of SPI FLASH is connected with the internal IO pin of RPMC, and the internal mutual communication between the SPI FLASH and the RPMC is achieved through the mutually connected internal IO pins. Thus, it is possible to reduce the package size, decrease the cost of design, shorten design period and improve chip performance.

SPI interface enhanced flash chip and chip packaging method

An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH and a RPMC packaged integrally, wherein the same IO pins in the FLASH and in the RPMC are mutually connected and are connected to the same external sharing pin of the chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pin of the chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; and the FLASH and the RPMC further comprise internal IO pins, respectively, the internal IO pins of the FLASH and the internal IO pins of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected internal IO pins.

Enhanced flash chip and method for packaging chip

An enhanced Flash chip and a method for packaging chip, wherein the enhanced Flash chip comprising: a FLASH and a RPMC, packaged integrally; the FLASH and the RPMC each comprising: a first internal IO pin and a second internal IO pin; the FLASH and the RPMC being further provided with a jumper window, one end of which is mutually connected to the first internal IO pin of the FLASH or the RPMC and the other end of which is mutually connected to the first internal IO pin of the RPMC or the FLASH; the second internal IO pin of the FLASH and the second internal IO pin of the RPMC being mutually connected. The enhanced Flash chip provided in the present application may effectively reduce design complexity and chip manufacturing cost, avoid the crossing of the metal lead wires in the chip package, and increase the yield of chip packages.

An adaptive block-matching motion estimator for used in a video coding system wherein the adaptive block-matching motion estimator is less in hardware complexity and latency time and is therefore more cost-effective to implement and higher in performance. This adaptive block-matching motion estimator includes a DS array for processing the pixel data of the current image block and the pixel data of the compared image block to thereby obtain a difference vector and a set of weight bits; a compression array having a first output port for outputting a compressed sum vector and a second output port for outputting an associated compressed carry vector, with the difference vector and the set of weight bits from the DS array along with the compressed sum vector and the associated compressed carry vector being taken as the inputs to the compression array; and a complexity-matching (CM) unit for processing the compressed sum vector and the associated compressed carry vector from the compression array to thereby produce the desired motion vector.

Adaptive block-matching motion estimator with a compression array for

A process for obtaining a motion vector for motion estimation used in a video image analysis, utilizing a block matching algorithm, which has the effect of reducing the computational load that is placed on the hardware logic used for implementation of the process. In a process of obtaining the absolute error value for the compared image block, a preliminary comparison is performed for every processed pixel in the image block to determine if the set minimum value of the absolute error function represented by a motionless tolerance constant is achieved. It is not necessary to obtain every actual value of the absolute error function. The block matching scheme of providing motion estimation enables hardware implementing the process to discontinue processing if the desired motion vector is selected prior to all image blocks being compared.

Motion estimation block matching process and apparatus for video image

An apparatus for implementing motion estimation block matching for video image processing. The apparatus receives pixel data of original and compared image blocks for comparison, to obtain an image motion vector. The apparatus has a multi-stage pipelined tree-architecture that includes a computation stage, a summation section, an accumulation stage, and a minimum value evaluation stage. The computation stage includes 2.sup.n computation members for producing a difference error value and a sign bit of the compared image blocks. The summation section coupled at the pipelined stage next to the computation stage, includes a series of summation stages for producing an absolute error value of the compared image blocks. A following accumulation stage adds an output of the single adder means of the last summation stage and a last un-added sign bit, for producing a sum. A last minimum value evaluator evaluates and generates the minimum of the output of the accumulation stage, as the motion vector for the implementation of motion estimation block matching for video image processing. Only a single adder is required in each of the computation members to reduce both the complexity and the processing delay for increased performance.

Growing community of inventors

Beijing, China

Qingming Shu