Freescale Semiconductor,inc.

Qingchun He

Peng Liu

Ping Wu

Hanmin Zhang

Liqiang Xu

Zhijie Wang

Ting Li

Nan Xu

Zhe Li

Zhaobin Qi

Tong Zhao

Jie Yang

Guanhua Wang

Yongqiang Liu

A packaged semiconductor device, such as a power QFN device, has (rectangular) ribbon wires, instead of circular bond wires. A proximal end of each ribbon wire is connected to a pad on an IC die, and a distal end of each ribbon wire forms a device lead. The die and the ribbon wires are encapsulated in a molding compound with a side of each device lead exposed. Such devices can be assembled without using lead frames. The omission of lead frames and the use of ribbon wires enable assembly of smaller devices having enhanced thermal dissipation capabilities.

Packaged semiconductor devices having ribbon wires

A semiconductor device includes a lead frame having a die support area and a plurality of inner and outer row leads surrounding the die support area, and a semiconductor die mounted on the die support area and electrically connected to the leads with bond wires. A molding material encapsulates the semiconductor die, the bond wires, and the leads, and defines a package body. The semiconductor device further includes connection bars extending vertically from the leads to a top surface of the package body. The connection bars connect the inner row leads to respective ones of the outer row leads before the molding process is performed.

Semiconductor device and lead frame having vertical connection bars

A method for assembling a quad flat no-lead (QFN) device includes mounting and electrically connecting a die to a pre-plated lead frame (PPF) to form a sub-assembly, where the plating is solder-wettable and the lead frame has notches in the lead fingers located along the device boundary. The sub-assembly is then encapsulated to (1) leave the distal ends of the lead fingers exposed and (2) have the edge of the encapsulant adjacent to the notches. The sub-assembly is then singulated to leave distal lead segments protruding from the resulting device. The protruding exposed segments are then bent to be substantially parallel to the device sidewalls. Consequently, the plated surface of each lead extends along portions of both the bottom and one side of the device.

Packaged integrated circuit device having bent leads

A semiconductor device includes a lead frame having a down bond area, a die attach area and a dam formed between the down bond area and the die attach area. A bottom of the dam is attached on a surface of the lead frame. The dam prevents contamination of the down bond area from die attach material, which may occur during a die attach process.

Semiconductor device and method of assembling same

An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

Brace for long wire bond

A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.

Method of making chip-on-lead package

A semiconductor package is assembled using first and second lead frames. The first lead frame includes a die flag and the second lead frame includes lead fingers. When the first and second lead frames are mated, the lead fingers surround the die flag. Side surfaces of the die flag are partially etched to form an extended die attach surface on the die flag, and portions of the top surface of each of the lead fingers also are partially etched to form lead finger surfaces that are complementary with the etched side surfaces of the die flag. A semiconductor die is attached to the extended die attach surface and bond pads of the semiconductor die are electrically connected to the lead fingers. An encapsulating material covers the die, electrical connections, and top surfaces of the die flag and lead fingers.

Semiconductor package and lead frame therefor

A lead frame sheet made of an electrically conductive material has lead frames integrally formed on it. Spacing members also are formed from the sheet. A first one of the spacing members is proximal to a first longitudinal edge of the sheet and a second one of the spacing members is proximal to a second longitudinal edge of the sheet. The spacing members extend from an underside surface of the sheet and, in use, space the underside surface from a planar support such as a surface of a heating block.

Lead frame sheet

A method of making semiconductor devices includes producing an array of first lead frames having rows of first electrical contact elements on respective sides. Sub-assemblies are produced by applying a first molding compound peripherally to provide support between the first electrical contact elements of each of the first lead frames, and singulating the sub-assemblies. An array of assemblies is produced, each of which includes a second lead frame having rows of second electrical contact elements on respective sides, a respective one of the sub-assemblies disposed in the second lead frame with the rows of first electrical contact elements nested adjacent to and inside the rows of second electrical contact elements, and a semiconductor die mounted on the sub-assembly. The assemblies are encapsulated using a second molding compound with the rows of first and second electrical contact elements exposed on adjacent sides of an active face of the respective assembly.

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Tianjin, China

Qingchun He