Intel Corporation

Other

Nanochip, Inc.

Qing Ma

Valluri Ramana Rao

Li-Peng Wang

Peng Cheng

Johanna M Swan

Quan Anh Tran

Feras Eid

John Heck

Tsung-Kuan Allen Chou

Harry H Fujimoto

Robert L Sankman

Quat T Vu

Kevin Lai Lin

Yuegang Zhang

Mineo Yamakawa

Weng Hong Teh

Jin Hyung Lee

Dong S Shim

Patrick R Morrow

Chun Mu

Paul B Fischer

Jian Li

Andrew A Berlin

Xiao-Chun Mu

Aleksandar Aleksov

John Stephen Guzek

Chuan Hu

Krishna Seshan

Nathan Franklin

Robert Starkston

Jun He

Charles A Gealer

Sridhar Balakrishnan

Travis M Eiles

Changhong Dai

Guanghai Xu

Steve Towle

Satish Radhakrishnan

Shiuh-Wuu Lee

Chia-Pin Chiu

Xing Su

Ebrahim Andideh

Kramadhati V Ravi

Richard O Jones

Larry E Mosley

Tae-Woong T Koo

Steven N Towle

Jose A Maiz

Lei B Sun

Jingwu Zhang

Tatyana N Andryushchenko

Jim Maveety

Min Tao

Byong Man Kim

Andy Berlin

Maria V Henao

Xintian Eddie Lin

William J Lambert

Robert J Chen

Giang T Dao

Helia A Naeimi

Kyu S Min

Chuanbin Pan

Eliav Zipper

Edward A Zarbock

Donald E Adams

Hanan Bar

Roy Swart

Robert N Stark

Eyal Bar-sadeh

Boaz Weinfeld

Tyler N Osborn

Michael DiBattista

Jun F Zheng

Michele J Berry

Yevgeny Anoikin

Daniel M Wong

Joseph S Hayden, Iii

Goutam Paul

Al Bettner

Israel Yankovich

Seth Fortuna

Edward T Zarbock

John E Evert

Tatyana T Adryushchenko

Lise Varner

John Carruthers

Semeon Altshuler

Joseph Melki

A semiconductor package having an air pressure sensor and methods to form a semiconductor package having an air pressure sensor are described. For example, a semiconductor package includes a plurality of build-up layers. A cavity is disposed in one or more of the build-up layers. An air pressure sensor is disposed in the plurality of build-up layers and includes the cavity and an electrode disposed above the cavity.

Semiconductor package with air pressure sensor

An electronic device and methods including a switch formed in a chip package are shown. An electronic device and methods including a switch formed in a polymer based dielectric are shown. Examples of switches shown include microelectromechanical system (MEMS) structures, such as cantilever switches and/or shunt switches.

Package MEMS switch and method

A method of manufacturing an accelerometer, including placing a magnet on a substrate, laminating a dielectric layer over the magnet, forming a conductive layer over the dielectric layer, the conductive layer including a mass and a conductive path overlying the magnet, removing a portion of the dielectric layer proximate the mass and conductive path such that the mass is movable in response to acceleration of the accelerometer, and forming a dielectric layer over the mass to form a space between the mass and the dielectric layer formed over the mass sufficiently clear such that the mass remains movable.

Method of making an accelerometer

A glass core substrate for an integrated circuit (IC) device may be formed to include a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Method of making glass core substrate for integrated circuit devices

Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing structure formed separately from a trace routing structure, wherein the glass routing structure is incorporated with the trace routing substrate, either in a laminated or embedded configuration. Also disclosed are embodiments of a microelectronic package including at least one microelectronic device disposed proximate to the glass routing structure of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects. Further, disclosed are embodiments of a microelectronic structure including at least one microelectronic device embedded within a microelectronic encapsulant having a glass routing structure attached to the microelectronic encapsulant and a trace routing structure formed on the glass routing structure.

Microelectronic structures having laminated or embedded glass routing structures for high density packaging

Embodiments of the present description relate to the field of fabricating microelectronic substrates. The microelectronic substrate may include a trace routing structure disposed between opposing glass layers. The trace routing structure may comprise one or more dielectric layers having conductive traces formed thereon and therethrough. Also disclosed are embodiments of a microelectronic package including a microelectronic device disposed proximate one glass layer of the microelectronic substrate and coupled with the microelectronic substrate by a plurality of interconnects.

Glass clad microelectronic substrate

Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers that have been bonded together. A separate bonding layer may be disposed between adjacent glass layers to couple these layers together. The substrate may also include build-up structures on opposing sides of the multi-layer glass core, or perhaps on one side of the core. Electrically conductive terminals may be formed on both sides of the substrate, and an IC die may be coupled with the terminals on one side of the substrate. The terminals on the opposing side may be coupled with a next-level component, such as a circuit board. One or more conductors extend through the multi-layer glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the core. Other embodiments are described and claimed.

Substrate for integrated circuit devices including multi-layer glass core and methods of making the same

Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.

Glass core substrate for integrated circuit devices and methods of making the same

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a microfluidic die to a package structure, wherein the microfluidic die comprises a plurality of asymmetric electrodes that may be coupled with signal pads disposed within the package structure.

Heterogeneous integration of microfluidic devices in package structures

Embodiments of the present disclosure are directed towards techniques and configurations for integrated circuit package assemblies including a glass solder mask layer and/or bridge. In one embodiment, an apparatus includes one or more build-up layers having electrical routing features and a solder mask layer composed of a glass material, the solder mask layer being coupled with the one or more build-up layers and having openings disposed in the solder mask layer to allow coupling of package-level interconnect structures with the electrical routing features through the one or more openings. Other embodiments may be described and/or claimed.

Integrated circuit package assemblies including a glass solder mask layer

Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermetically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.

Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips

The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.

Debond interconnect structures

Growing community of inventors

San Jose, CA, United States of America

Qing Ma