Chinese Academy of Sciences

Beijing Didi Infinity Technology and Development Co., Ltd.

Beijing Jingdong Shangke Information Technology Co., Ltd.

Beijing Jingdong Century Trading Co., Ltd.

Qing Luo

Ming Liu

Hangbing Lv

Xiaoxin Xu

Hao Zhang

Changqing Xie

Dongmei Li

Cheng Lu

Xiaojing Li

Shengfa Liang

Zheng Wang

Qi Liu

Shibing Long

Bing Chen

Tiancheng Gong

Yu Liu

Xin Chen

Jiebin Niu

Shuang Zhan

Peiwen Zhang

Tienan Jiang

Hongzhang Yang

Zhiyuan Zhong

A complementary storage unit and a method of preparing the same, and a complementary memory. The complementary storage unit includes: a control transistor, a pull-up diode and a pull-down diode. The control transistor is configured to control reading and writing of the storage unit. One end of the pull-up diode is connected to a positive selection line, and the other end thereof is connected to a source end of the control transistor, so as to control a high-level input. One end of the pull-down diode is connected to a negative selection line, and the other end thereof is connected to the source end of the control transistor, so as to control a low-level input. The pull-up diode and the pull-down diode are symmetrically arranged in a first direction.

Complementary storage unit and method of preparing the same, and complementary memory

Provided are a symmetric memory cell and a BNN circuit. The symmetric memory cell includes a first complementary structure and a second complementary structure, the second complementary structure being symmetrically connected to the first complementary structure in a first direction, wherein the first complementary structure includes a first control transistor configured to be connected to the second complementary structure, the second complementary structure includes a second control transistor, a drain electrode of the second control transistor and a drain electrode of the first control transistor being symmetrically arranged in the first direction and connected to a bit line, and the symmetric memory cell is configured to store a weight value 1 or 0.

Symmetric memory cell and BNN circuit

Disclosed is a neural network operation device, including: an operation array including operation units, wherein each operation unit includes: a source terminal, a drain terminal, a gate electrode, a threshold voltage adjustment layer under the gate electrode, and a channel region extending between a source region and a drain region, the threshold voltage adjustment layer is located on the channel region. The gate electrodes of each column of operation units of the operation array are connected together, and each column is used to adjust a weight value according to a threshold voltage adjusted by the threshold voltage adjustment layer. The threshold voltage adjustment layer is a ferroelectric layer.

Neural network operation device

A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

Writing method and erasing method of fusion memory

The present disclosure provides a fusion memory including a plurality of memory cells, wherein each memory cell of the plurality of memory cells includes: a bulk substrate; a source and a drain on the bulk substrate; a channel extending between the source and the drain; a ferroelectric layer on the channel; and a gate on the ferroelectric layer.

Fusion memory

The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.

Self-rectifying resistive memory and fabrication method thereof

A method for determining an estimated time of arrival (ETA) may include obtaining a service request from a terminal and determining a reference image relating to the service request. The method may also include obtaining a trained neural network model. The method may further include determining an ETA relating to the service request based on the reference image and the trained neural network model, and transmitting the ETA to the terminal.

Systems and methods for determining an estimated time of arrival

The present disclosure provides a 1S1R memory integrated structure and a method for fabricating the same, wherein the 1S1R memory integrated structure includes: a word line metal, a resistive material layer, a selector lower electrode, a selector material layer, a selector upper electrode, an interconnection wire, and a bit line metal; wherein the selector material layer is in a shape of a groove, and the selector upper electrode is formed in the groove. According to the 1S1R memory integrated structure and its fabricating method in the present disclosure, by the change of the integrated position of the selector, the device area of the selector is much larger than the device area of the memory, which significantly reduces the requirement for the on-state current density of the selector.

1S1R memory integrated structure with larger selector surface area which can effectively suppress leakage current in the cross array without increasing the overall size of the integrated structure and method for fabricating the same

A method for determining an estimated time of arrival (ETA) includes receiving a start location and a destination from a user device via a network. The method also includes obtaining a machine learning model for determining an ETA, which is generated according to a process including: obtaining historical data related to an on-demand service order; determining a high-dimensional sparse feature based on the historical data; and determining a machine learning model based on the high-dimensional sparse feature. The method further includes determining an ETA for a target route based on the machine learning model, the start location, and the destination, and transmitting the determined ETA to the user device via the network.

Systems and methods for determining estimated time of arrival

A system and method for processing a screenshot-type note of a streaming document. The system comprises: a gesture processing module () for recording screen coordinates of a selected region in a pre-set shape determined by a gesture in a current page of the streaming document; a note position calculation module () for receiving the screen coordinates of the selected region in the pre-set shape, and converting a screen coordinate of a pre-set position in the selected region into a relative position of a leaf node in the streaming document; and a note information storage module () for storing the relative position of the leaf node and the screen coordinates of the selected region as note position information. The technical solution can improve the accuracy of a display position of a screenshot-type note in a streaming document.

System and method for processing screenshot-type note of streaming document

Provided are a self-gating resistive storage device and a method for fabrication thereof; said self-gating resistive storage device comprises: lower electrodes; insulating dielectric layers arranged perpendicular to, and intersecting with, the lower electrodes to form a stacked structure, said stacked structure being provided with a vertical trench; a gating layer grown on the lower electrodes by means of self-alignment technique, the interlayer leakage channel running through the gating layer being isolated via the insulating dielectric layers; a resistance transition layer arranged in the vertical trench and connected to the insulating dielectric layers and the gating layer; and an upper electrode arranged in the resistance transition layer. In the storage device provided by the described technical solution, the gating layer is grown on the lower electrodes by means of self-alignment technique, such that the interlayer leakage channel running through the gating layer is isolated via the insulating dielectric layers; thus leakage between the upper and lower word lines through the gating layer is prevented, solving the technical problem in the prior art of leakage between the upper and lower word lines in a self-gating resistive storage device, and improving the reliability of the device.

Self-gating resistive storage device having resistance transition layer in vertical trench in stacked structure of insulating dielectric layers and electrodes

A selector for a bipolar resistive random access memory and a method for fabricating the selector are provided. The method includes: providing a substrate; forming a lower electrode on the substrate, where the lower electrode is made of a metal, and the metal is made up of metal atoms which diffuse under an annealing condition of below 400&#xb0; C.; forming a first metal oxide layer on the lower electrode; performing an annealing process on the first metal oxide layer to make the metal atoms in the lower electrode diffuse into the first metal oxide layer to form a first metal oxide layer doped with metal atoms; forming a second metal oxide layer on the first metal oxide layer doped with metal atoms; forming an upper electrode layer on the second metal oxide layer; and patterning the upper electrode layer to form an upper electrode.

Selection device for use in bipolar resistive memory and manufacturing method therefor

A sampler adapted to a one-dimension slow-varying signal, including: a signal preprocessing unit configured to preprocess an input signal; a slope-controllable sawtooth wave signal generating unit configured to generate a slope-controllable sawtooth wave signal and perform zero-resetting; a signal comparing unit configured to compare the preprocessed input signal from the signal preprocessing unit with the sawtooth wave signal and to output a pulse signal to the generating unit and a signal outputting unit when the preprocessed input signal is equal to the sawtooth wave signal; a counting unit configured to count a number of clock signals while the sawtooth wave signal generating unit is generating the sawtooth wave signal and to transmit the counted number to the signal outputting unit; the signal outputting unit configured to, upon receipt of the pulse signal output from the signal comparing unit, output the number counted by the counting unit at the moment.

Random sampler adapted to one-dimension slow-varying signal

A method for collecting a signal with a frequency lower than a Nyquist frequency includes, by a data transmitting end, selecting a suitable transformation base matrix for an input signal, deriving a sparse representation of the signal using the transformation base matrix to determine a sparsity of the signal, calculating a number M of compressive sampling operations according to the sparsity, sampling the signal with fusing M channels, and integrating sampling values of each channel to obtain M measurement values. A reconstruction end reconstructs an original signal by solving optimization problems. Based on theory, compressive sampling can be performed on a sparse signal or a signal represented in a sparse manner with a frequency much lower than the Nyquist frequency, overcoming restrictions of the typical Nyquist sampling theorem. The method can be implemented simply and decrease pressure on data collection, storage, transmission and processing.

Method for collecting signal with sampling frequency lower than Nyquist frequency

The present disclosure provides a method for manufacturing ordered nanowires array of NiO doped with Pt in situ, comprising: growing a Ni layer on a high-temperature resistant and insulated substrate; applying a photoresist on the Ni layer, pattering a pattern region of the ordered nanowires array by applying electron beam etching on the photoresist, growing Ni on the pattern region of the ordered nanowires array, peeling off the photoresist by acetone and etching the surface of the Ni layer by ion beam etching so as to etch off the Ni layer grown on the surface of the substrate and to leave the Ni on the pattern region of the ordered nanowires array to form the ordered Ni nanowires array; dipping the ordered Ni nanowires array into a solution of HPtClso as to displace Pt on the Ni nanowires array by a displacement reaction; and oxidizing the Ni nanowires array attached with Pt in an oxidation oven to obtain the ordered nanowires array of NiO doped with Pt. The present invention is simple and practical and the sensitivity and reliability of the doped sensor on the gas of CO and Hare greatly improved.

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Beijing, China

Qing Luo