Yangtze Memory Technologies Co., Ltd.

Qiang Tang

Chunyuan Hou

Jason Guo

Xiang Fu

Min She

Weirong Chen

Shuang Shuang Li

Haibo Li

Yu Wang

Daesik Song

Ke Liang

Chun Yuan Hou

Khanh Nguyen

Li Wei Wang

Sangoh Lim

Jiawei Chen

Shuang Li

Qing Ruan

A system includes multiple memory dies. Each of the memory dies includes a PPM circuit including a first pull driver, a second pull driver, and a PPM contact pad connected between the first pull driver and the second pull driver. The PPM contact pads of the multiple memory dies are electrically connected with each other. The PPM circuits of the multiple memory dies are configured to manage peak power operations according to a first pull current flowing through a certain first pull driver of a certain PPM circuit. The first pull current is a sum of second pull currents flowing through second pull drivers of the PPM circuit. Each of the second pull currents is proportional to a current level of a corresponding memory die.

Dynamic peak power management for multi-die operations

In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes P groups of banks. Each group of banks includes N main banks and M redundant banks, where each of P, N and M is a positive integer, and N is greater than M. The I/O circuit is coupled to the P groups of banks and configured to direct P×N pieces of data to or from P×N working banks, respectively. One of the M redundant banks is coupled with at least two main banks of the N main banks through the I/O circuit. The I/O control logic is configured to in responding to K main banks of the P groups of banks failed, determine the P×N working banks including K redundant banks of P×M redundant banks, where K is a positive integer not greater than P, and control the I/O circuit to direct P×N pieces of data to or from the P×N working banks, respectively.

Memory device with failed main bank repair using redundant bank

A method of programming a ferroelectric memory device is disclosed. The method includes applying a first voltage to a first word line; applying a second voltage to the first word line; and applying a pass voltage to a second word line during a period of applying the first voltage to the first word line and during a period of applying the second voltage to the first word line. The pass voltage is between the first threshold voltage and the second threshold voltage.

Method for reading and writing memory cells in three-dimensional FeRAM

A memory device includes a string of cells having one and more top selection cells, one or more dummy memory cells, and memory cells, and a peripheral circuit coupled to the string of cells. The peripheral circuit is configured to verify a threshold voltage of at least one of the one or more top selection cells or the one or more dummy memory cells to determine whether the at least one of the one or more top selection cells or the one or more dummy memory cells has failed. In response to the at least one of the one or more top selection cells or the one or more dummy memory cells being failed, the peripheral circuit is further configured to reset the at least one of the one or more top selection cells or the one or more dummy memory cells.

Memory device capable of reducing program disturbance and erasing method thereof

A three-dimensional (3D) memory device and a fabricating method for forming the same are disclosed. The 3D memory device can include an alternating conductor/dielectric layer stack disposed on a substrate, a first staircase structure and a second staircase structure formed in the alternating conductor/dielectric layer stack, a staircase bridge extending in a first direction and electrically connecting the first staircase structure and the second staircase structure, and a first bottom select gate segment covered or partially covered by the staircase bridge. The first bottom select gate segment can include an extended portion extending in a second direction different from the first direction.

Bottom select gate contacts for center staircase structures in three-dimensional memory devices

A memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one first word line structure. The first memory array is disposed between the first substrate and the second substrate in a vertical direction. The first vertical transistor is electrically connected with the first word line structure. At least a part of the at least one first vertical transistor is disposed in the second substrate.

Memory device

A 3D flash memory device includes a substrate having a substantial planar surface. A plurality of active columns of semiconducting material is disposed above the substrate. Each of the plurality of active columns extends along a first direction orthogonal to the planar surface of the substrate. The plurality of active columns is arranged in a two-dimensional array. Each of the plurality of active columns may comprise multiple local bit lines and multiple local source lines extending along the first direction. Multiple channel regions are disposed between the multiple local bit lines and multiple local source lines. A word line stack wraps around the plurality of active columns. A charge-storage element is disposed between the word line stack and each of the plurality of active columns.

Three-dimensional flash memory device with increased storage density

In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes P groups of banks. P redundant banks are included in and shared by the P groups of banks. The I/O circuit is coupled to the P groups of banks and configured to direct P×N pieces of data to or from P×N working banks, respectively. The I/O control logic is configured to determine the P×N working banks from the P groups of banks based on bank fail information indicative of K failed main banks from the P groups of banks. The P×N working banks include K redundant banks of the P redundant banks. The I/O control logic is also configured to control the I/O circuit to direct P×N pieces of data to or from the P×N working banks, respectively.

A method of peak power management (PPM) is provided for two NAND memory dies. each NAND memory die comprises a PPM circuit having a PPM contact pad held at an electric potential common between the two NAND memory dies. The method includes the following steps: detecting the electric potential during a first peak power check (PPC) routine for the first NAND memory die; driving the electric potential to a second voltage level if the detected electric potential is at a first voltage level higher than the second voltage level; generating a pausing signal in the electric potential to pause a second PPC routine for the second NAND memory die if no pausing signal is detected; and generating a resuming signal in the electric potential to resume the second PPC routine for the second NAND memory die after the first NAND memory die completes a first peak power operation.

Memory system and peak power management for memory dies of the memory system

A method of peak power management (PPM) for a storage system with multiple memory dies is provided, where each of the multiple memory dies includes a PPM circuit having a PPM contact pad and PPM contact pads of the multiple memory dies are electrically connected. The PPM method includes the following steps: switching on a pull-down driver of the PPM circuit on a selected memory die of the storage system; verifying a PPM enablement signal regulated by a pull-down current flowing through the pull-down driver; and performing a peak power operation on the selected memory die when the PPM enablement signal indicates that a total current of the storage system is less than a maximum total current allowed for the storage system.

In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes a first-level memory unit which includes a plurality of second-level memory units. Each second-level memory unit includes N main banks and a redundant bank, where N is a positive integer. The I/O circuit is configured to direct N pieces of data to or from N working banks in a corresponding second-level memory unit. The I/O control logic is configured to determine the N working banks from the N main banks and the redundant bank in the corresponding second-level memory unit based on bank fail information indicative of a failed main bank of the N main banks and control the I/O circuit to direct the N pieces of data to or from the N working banks, respectively.

Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, the 3D memory device includes a film stack having a plurality of conductive and dielectric layer pairs vertically stacked on a substrate. Each conductive and dielectric layer pair includes a dielectric layer and a conductive layer. The 3D memory device also includes a staircase region having a first and a second staircase structure formed in the film stack, where the first and second staircase structures each extends laterally in a first direction and includes the plurality of conductive and dielectric layer pairs. The staircase region further includes a staircase bridge connecting the first and second staircase structures.

Staircase bridge structures for word line contacts in three-dimensional memory

A programming method for a three-dimensional ferroelectric memory device is disclosed. The programming method includes applying a first voltage on a selected word line of a target memory cell. The target memory cell has a first logic state and a second logic state corresponding to a first threshold voltage and a second threshold voltage, respectively. The first and second threshold voltages are determined by two opposite electric polarization directions of a ferroelectric film in the target memory cell. The programming method also includes applying a second voltage on a selected bit line, where a voltage difference between the first and second voltages has a magnitude larger than a coercive voltage of the ferroelectric film such that the target memory cell is switched from the first logic state to the second logic state.

A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

A bias circuit, a memory system, and a method of boosting a voltage level of a first bit line are provided. The bias circuit includes a first current generator, a second current generator, and a bit line bias generator. The first current generator is configured to generate a first replica charging current according to a charging current flowing through a voltage bias transistor. The second current generator is configured to generate a first replica cell current according to a cell current flowing through a common source transistor. The bit line bias generator is coupled to a first page buffer, the first current generator, and the second current generator, and configured to generate a bit line bias voltage, supplied to the first page buffer, according to a comparison of the first replica charging current and the first replica cell current.

Growing community of inventors

Wuhan, China

Qiang Tang