Changxin Memory Technologies, Inc.

Qian Xu

Tieh-chiang Wu

Lingxin Zhu

Pan Mao

Junjie Liu

Yingtao Zhang

Bin Song

Liang Wang

Bo Yang

Zhan Xue

Xinyu Huang

Hang Yang

An anti-fuse circuit includes the following: a first transistor, and at least one parasitic transistor and at least one parasitic triode that are connected to the first transistor. The at least one parasitic transistor and the at least one parasitic triode are connected to a first node.

Simulation test model for anti-fuse circuit and circuit testing method

An electrostatic discharge protection circuit includes: a pulse detection unit, a delay unit, a control unit, and a discharge unit. The pulse detection unit is configured to detect an electrostatic pulse signal; the delay unit is configured to delay or enhance driving capability of the pulse detection signal output by the pulse detection unit; the control unit is configured to generate a control signal based on a first delay signal and a second delay signal output by the delay unit; and the discharge unit is configured to open or close an electrostatic charge discharge passage based on the control signal output by the control unit.

Electrostatic discharge protection circuit including a pulse detection circuit

The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

ESD protection structure, ESD protection circuit, and chip

The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

Electro-static discharge protection structure and chip

An electrostatic protection circuit includes: a monitoring circuit configured to generate a trigger signal in response to an electrostatic pulse being present on the power supply pad; a discharge transistor connected between the power supply pad and the ground pad and configured to be turned on under control of the trigger signal and discharge electrostatic discharging charges to the ground pad; and a delay circuit having an input terminal connected to an output terminal of the monitoring circuit, and an output terminal connected to a control terminal of the discharge transistor, where the delay circuit is configured to perform delay processing on the electrostatic protection circuit in a first state and turn off the discharge transistor in a second state.

Electrostatic protection circuit

The present disclosure provides an electrostatic protection device, and relates to the technical field of semiconductors. The electrostatic discharge protection device includes a first P-type heavily-doped region, a first N-type heavily-doped region, a second N-type heavily-doped region, a second P-type heavily-doped region, and a third N-type heavily-doped region. The first P-type heavily-doped region and the first N-type heavily-doped region are located in a P well, the second P-type heavily-doped region and the third N-type heavily-doped region are located in a first N well, one part of the second N-type heavily-doped region is located in the P well, the other part of the second N-type heavily-doped region is located in first N well, and the P well and the first N well are adjacent to each other and both located in the P-type substrate.

Electrostatic discharge protection device

The present disclosure provides a latch-up test structure, including: a substrate of a first conductive type; a first well region of the first conductive type, located in the substrate of the first conductive type; a first doped region of the first conductive type, located in the first well region of the first conductive type; a first doped region of a second conductive type, located in the first well region of the first conductive type; and a second doped region of the first conductive type, a second doped region of the second conductive type, a third doped region of the first conductive type, and a third doped region of the second conductive type that are arranged at intervals in the substrate of the first conductive type.

Latch-up test structure

A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate including a plurality of pads spaced apart from each other, a first groove, and a second groove connected with the first groove, the first and the second grooves located in the substrate. The first groove is located on the side of the second groove away from the plurality of pads, and the bottom of the second groove exposes a corresponding pad of the plurality of pads. The orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate. A redistribution layer is disposed on a surface of the corresponding pad, the inner wall of the first groove, and the inner wall and the bottom of the second groove. The semiconductor structure prevents contamination or damage of test probes.

Semiconductor structure and method of manufacturing same

Embodiments of the disclosure provide a capacitance measurement method, system and apparatus, an electronic device, and a storage medium. The method is applied to a machine table and includes: obtaining a calibration file including multiple first capacitance values corresponding to a measurement probe card while the measurement probe card is floating; measuring, by the measurement probe card, multiple semiconductor devices simultaneously to obtain multiple second capacitance values corresponding to the multiple semiconductor devices, the multiple semiconductor devices being located on a same test module of a semiconductor chip; and determining target capacitance values of the multiple semiconductor devices based on the multiple first capacitance values and the multiple second capacitance values.

Capacitance measurement method, system and apparatus, electronic device, and storage medium

Provided is an electrostatic discharge protection device, including: a darlington structure formed in a substrate, and a diode string formed in the substrate and including a plurality of diodes connected in series. A first end of the darlington structure is connected to a first voltage, and a second end of the darlington structure is connected to a second voltage. An anode of the diode string is connected to a third end of the darlington structure. A cathode of the diode string is connected to the second voltage.

Embodiments of the present disclosure relate to an electrostatic protection structure and an electrostatic protection circuit. The electrostatic protection structure includes: a SCR structure and a trigger structure; the SCR structure includes: a well region of a second conductivity type and a first well of a first conductivity type region, a first-doped region of the first conductivity type, and a first-doped region of the second conductivity type; the trigger structure includes: a first-doped region of the second conductivity type, a second well region of the first conductivity type, a second-doped region of two conductivity types, a third-doped region of the second conductivity type, a fourth-doped region of the second conductivity type, and a first gate electrode. The electrostatic protection structure weakens the positive feedback of the parasitic transistor in the SCR device, improves the anti-latch capability of the device, realizes stronger protection capability, and enhances the reliability of the circuit.

Electrostatic protection structure and electrostatic protection circuit

The present disclosure provides a diode-triggered bidirectional silicon controlled rectifier and circuit. The silicon controlled rectifier includes: a P-type substrate; a first P well formed in the P-type substrate, a first P-type doped region and a first N-type doped region being formed in the first P well; a second P well formed in the P-type substrate, a third N-type doped region and a fourth P-type doped region being formed in the second P well; and an N well formed in the P-type substrate, a second P-type doped region, a second N-type doped region and a third P-type doped region being formed in the N well. The second N-type doped region is electrically connected with a positive electrode of a diode string, and the first P-type doped region and the fourth P-type doped region are electrically connected with a negative electrode of the diode string.

Diode-triggered bidirectional silicon controlled rectifier and circuit

Embodiments provide an electrostatic discharge (ESD) protection circuit and an electrostatic discharge method. The ESD protection circuit includes: a pulse detection unit (), a discharge transistor (), a feedback delay unit (), and a processing unit (). A first terminal of the pulse detection unit () is connected to a first pad (), a second terminal of the pulse detection unit () is connected to a second pad (), and an output terminal of the pulse detection unit () is configured to output a detection result signal. A gate of the discharge transistor () is connected to the output terminal of the pulse detection unit (), a drain of the discharge transistor () is connected to the first pad (), and a source of the discharge transistor () is connected to the second pad (). The feedback delay unit () includes a PMOS transistor (Mp) and an NMOS transistor (Mn).

Electrostatic discharge (ESD) protection circuit, integrated circuit, and electrostatic discharge method

A method for identifying a latch-up structure includes the following: in a chip layout, a first N-type heavily doped region connected to a first input/output pad and located in a P-type substrate is found; a first P-type heavily doped region located in an N-well and a second P-type heavily doped region located in the P-type substrate, both of which are adjacent to the first N-type heavily doped region, are found; a second N-type heavily doped region adjacent to the first P-type heavily doped region and located in the N-well is found, wherein the N-well is located on the P-type substrate; and an area formed by the first P-type heavily doped region, the first N-type heavily doped region, the second P-type heavily doped region, the second N-type heavily doped region, the N-well and the P-type substrate is identified as the latch-up structure.

Method for identifying latch-up structure

A method for evaluating a Hot Carrier Injection (HCI) effect of a device is provided. The method includes, a ratio of a substrate current to a drain current of a first device at different gate-source voltages is acquired, and recorded as a first current ratio; a ratio of a substrate current to a drain current of a second device at different gate-source voltages is acquired, and recorded as a second current ratio, the second device is subjected to process parameter adjustment or device parameter adjustment relative to the first device; and an influence of the process parameter adjustment or the device parameter adjustment on an HCI effect of the device is determined based on the second current ratio and the first current ratio.

Growing community of inventors

Hefei, China

Qian Xu