Texas Instruments Corporation

International Business Machines Corporation

Qi-Zhong Hong

Wei-Yung Hsu

Abbas Ali

Dhishan Kande

Robert H Havemann

Jiong-Ping Lu

Gregory Boyd Shinn

Shin-Puu Jeng

Lawrence Alfred Clevenger

Cyril Cabral, Jr

Girish Anant Dixit

Honglin Guo

Jorge Adrian Kittl

Young-Joon Park

Jorge A Kittl

Francedillaois Max d'Heurle

Kyle McPherson

Benjamin James Timmer

Bhaskar Srinivasan

Jeffrey Alan West

Matthew Warren Copel

William R McKee

Paul David Agnello

Manoj K Jain

Ting Yiu Tsui

Robert Yung-Hsi Tsu

Changming Jin

Duane E Carter

Tz-Cheng Chiu

Richard Allen Faust

Anthony J Konecni

Eden M Zielinski

Shouli Steve Hsia

Francois M d'Heurle

Shih Chang Chang

David Permana

Lu Zhijian

Joseph Jian Song

Peter Huang

Vincent T Cordasco

Yung Liu

An electronic device includes a semiconductor die having a multilevel metallization structure including stacked levels with respective dielectric layers and metal lines, and a low leakage, low hydrogen diffusion barrier layer on one of the stacked levels. The diffusion barrier layer contacts a side of the dielectric layer and the metal line of the one of the stacked levels, and the diffusion barrier layer includes silicon nitride material having a first bond percentage ratio of ammonia to silicon nitride that is greater than a second bond percentage ratio of silicon hydride to silicon nitride.

Dielectric silicon nitride barrier deposition process for improved metal leakage and adhesion

A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

Thin film resistor with punch-through vias

An integrated circuit (IC) includes a substrate having a semiconductor surface layer with functional circuitry for realizing at least one circuit function, with an inter level dielectric (ILD) layer on a metal layer that is above the semiconductor surface layer. A thin film resistor (TFR) including a TFR layer is on the ILD layer. At least one vertical metal wall is on at least two sides of the TFR. The metal walls include at least 2 metal levels coupled by filled vias. The functional circuitry is outside the metal walls.

IC with thin film resistor with metal walls

A method of fabricating integrated circuits (ICs) includes depositing a dielectric liner layer on a substrate including a semiconductor surface having a plurality of IC die formed therein each including functional circuitry including a plurality of interconnected transistors. A thin film resistor (TFR) layer including chromium (Cr) is deposited on the dielectric liner layer. The substrate is loaded into a hardmask layer deposition tool that includes a plasma source. The TFR layer is in-situ plasma pre-treated including flowing at least one inert gas and at least one oxidizing gas while in the hardmask layer deposition tool. A hardmask layer is deposited after the plasma pre-treating while remaining in the hardmask layer deposition tool. A pattern is formed on the hardmask layer, and the hardmask layer and TFR layer are etched stopping in the dielectric liner layer to form at least one resistor from the defined TFR layer.

In-situ plasma treatment for thin film resistors

A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.

Metal interconnect processing for an integrated circuit metal stack

A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect. A method of operating a computer system to improve via electromigration in an integrated circuit with multilevel interconnect using via priority groups.

Multilevel via placement with improved yield in dual damascene interconnection

A device and method for fabricating an integrated circuit (IC) chip is disclosed. The method includes depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; and patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor. The method continues with depositing a second ILD layer overlying the first resistor; and patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor. The etch retardant layer is selective to a first etch chemistry and the thickness of the etch retardant layer is such that the via etching process removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material.

Device and method for a thin film resistor using a via retardation layer

A method of fabricating an integrated circuit (IC) includes forming a metal interconnect stack on substrate that includes a plurality of product die each having a plurality of transistors connected together to implement a circuit function. The forming the metal interconnect stack includes depositing a metal interconnect layer comprising aluminum on a barrier layer at a first temperature. After depositing the metal interconnect layer, the metal interconnect stack is annealed in a non-oxidizing ambient at a maximum annealing temperature that is&#x3c;the first temperature. After the annealing, a pattern is formed on the metal interconnect layer, and at least the metal interconnect layer is etched.

Metal interconnect processing for a non-reactive metal stack

A dual damascene process employs a via fill material () with an etch rate that is within 60% of an etch rate that an underlying dielectric layer () etches for a given dielectric etch chemistry in which a trench () and via () are being formed. In one embodiment, an organic via fill material plug () is employed in conjunction with a bottom anti-reflective coating (BARC) material layer (). Both the organic via fill material plug () and the BARC material layer () are selected to have a material with an etch rate that within 60% of an etch rate that an underlying dielectric layer () etches for a given dielectric etch chemistry in which the trench () and via () are formed.

Method of eliminating etch ridges in a dual damascene process

Disclosed is a system for fabricating a semiconductor device (). An interconnect structure () is formed on the semiconductor device () and a cap () is deposited over the interconnect structure (). The interconnect structure () is annealed with the overlying cap () in place. The cap () is then removed after the interconnect structure () is annealed.

System for improving thermal stability of copper damascene structure

An embodiment of the invention is a method of manufacturing a semiconductor wafer where a layer of undoped silicon glass is formed over the front-end structure . Another embodiment of the present invention is an integrated circuit having a back-end structure in which the dielectric layer contains undoped silicon glass.

Semiconductor PMD layer dielectric

Growing community of inventors

Richardson, TX, United States of America

Qi-Zhong Hong