Advanced Micro Devices Corporation

Altera Corporation

Globalfoundries Inc.

Xilinx, Inc.

Advanced Micro Device, Inc.

Other

Lattice Semiconductor Corporation

Qi Xiang

Eric N Paton

Paul Raymond Besser

Matthew S Buynoski

Bin Yu

Ming-Ren Lin

Haihong Wang

Jung-Suk Goo

Jun Liu

Cyrus E Tabery

Robert B Ogle

Albert Ratnakumar

James N Pan

Wei Long

Paul L King

Minh Van Ngo

Jeffrey Xiaoqi Tung

George Jonathan Kluth

John C Foster

Witold P Maszara

Zoran Krivokapic

Scott Allan Bell

Irfan Rahim

Shekhar Pramanick

Chih-Yuh Yang

Yowjuang William Liu

Joong Jeon

Derick J Wristers

James F Buller

Olov B Karlsson

Andy Louie Lee

Huicai Zhong

Christy Mei-Chu Woo

Shankar Sinha

Xiao-yu Li

Minh-Van Ngo

Ming Lin

Jeffrey T Watt

Mahbub Rashed

Yanzhong Xu

Srinivas Perisetty

Shih-Lin S Lee

Sunil D Mehta

Jongwook Kye

Srinath Krishnan

Navneet Jain

Akif Sultan

Philip A Fisher

Simon Siu-Sing Chan

Allison Holbrook

Xiao-Yu Li

Geoffrey Choh-Fei Yeap

Glenn O'Rourke

Ihsan Djomehri

Niraj Subba

Wilson Wong

Sergey D Lopatin

Steven C Avanzino

Daniel Kadosh

Weiqi Ding

Lei Yuan

Dong-Hyuk Ju

David Donggang Wu

Simardeep Maangat

William Bradley Vest

Yow-Juang Bill Liu

Jacques J Bertrand

Cinti Xiaohua Chen

Yunfei Deng

Ercan Adem

Lu Zhou

David S Bang

David Doman

Bradley Jensen

Subash Gupta

Boon-Yong Ang

Robert B Clark-Phelps

Hidekazu Yoshida

Charu Sardana

Felino E Pagaduan

Farzad Arasnia

Paul D Mesa

Qinglei Wang

Mao Du

Thao H T Vo

Colman Wong

Matthew S Byunoski

Shiying Xiong

Yanzhong Yu

Cinti X Chen

An integrated circuit (IC) chip package assembly apparatus and techniques for assembling IC chip packages are described. For example, a techniques for fabricating an IC package include (A) determining a first package assembly yield (PAY) across a first die pool comprising a first plurality of dies having a performance criteria within a first predefined range; (B) determining a second PAY across a second die pool comprising a second plurality of dies having a performance criteria within a second predefined range of performance criteria that is different than the first predefined range of performance criteria, the second plurality of dies comprising a portion of the first plurality of dies; and (C) generating a final assembly sequence in response to analyzing the first and second PAYs, the final assembly sequence comprising rules for combining dies in accordance with obtaining a higher of the first PAY and the second PAY.

High yield package assembly technique

Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

Integrated circuits with asymmetric and stacked transistors

Integrated circuits with memory circuitry are provided. The memory circuitry may include memory cell transistors and associated pass transistors. The memory cell transistors and the pass transistors may be formed using multiple strips of oxide definition (OD) regions coupled in parallel. The multiple OD strips may have reduced widths. The ratio of the distance from adjacent OD strips to a given OD strip to the width of the given OD strip may be at least 0.5. Forming memory circuitry transistors using this multi-strip arrangement may provide increased levels of stress that improve transistor performance. Each OD strip may have a reduced width that still satisfies fabrication design rules. Forming OD regions having reduced width allows the pass transistors to be overdriven at higher voltage levels to further improve transistor performance.

Memory element circuitry with minimum oxide definition width

A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.

Semiconductor device having structure with fractional dimension of the minimum dimension of a lithography system

An apparatus relating generally to an interposer is disclosed. In such an apparatus, the interposer has a plurality of conductors and a plurality of charge attracting structures. The plurality of charge attracting structures are to protect at least one integrated circuit die to be coupled to the interposer to provide a stacked die. The plurality of conductors include a plurality of through-substrate vias.

Charge damage protection on an interposer for a stacked die assembly

A programmable device with a metal oxide semiconductor field effect transistor (MOSFET) surrounded by a programmable substrate region is described. The MOSFET has a source and drain region separated by a channel region with an insulating region and gate disposed above the channel region. A junction disposed within the substrate region controls the programmable substrate region. Biasing the junction depletes the substrate region, which isolates the body of the MOSFET from a secondary well. When the junction is left unbiased, the body of the MOSFET is electrically coupled to the secondary well.

Programmable device with a metal oxide semiconductor field effect transistor

Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

Method of fabricating integrated circuit transistors with multipart gate conductors

A method that includes using a PMOS pass gate to couple a first line to a second line, where a gate terminal of the PMOS pass gate is coupled to an output terminal of a memory cell, is described. In one implementation, the PMOS pass gate has a negative threshold voltage. In one implementation, the first line and the second line are respectively first and second interconnect lines of an IC.

Method of using a PMOS pass gate

An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

Integrating optimal planar and three-dimensional semiconductor design layouts

A parameterized cell for planar and finFET designs is provided. A parameterized cell (Pcell) describing a planar design is integrated with fin-based design criteria, including fin pitch. For material regions in a planar design that have a corresponding region in a fin design, a quantized value based on the fin pitch is computed. The material can include regions such as active area silicon, contact regions, and local interconnect regions.

Parameterized cell for planar and finFET technology design

An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.

PMOS pass gate

Integrated circuit transistors with multipart gate conductors

Integrated circuits and methods for fabricating integrated circuits are provided. One method includes creating a master pattern layout including first and second adjacent cells. The first adjacent cell has a first border pin with a first routing line. The second adjacent cell has a second border pin with a second routing line. The first and second routing lines overlap to define an edge-edge stitch to couple the first and second border pins. The master pattern layout is decomposed into sub-patterns.

Integrated circuits and methods for fabricating integrated circuits using double patterning processes

Memory element circuitry with reduced oxide definition width

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Qi Xiang