Intel Corporation

International Business Machines Corporation

Other

Pushkar Ranade

Wilfred Gomes

Keith Zawadzki

Vijay Narayanan

Cyril Cabral, Jr

Sufi Zafar

Deborah A Neumayer

Paul Charles Jamison

Christopher P Auth

Fenton Read McFeely

Alessandro Cesare Callegari

Michael Abramovich Gribelyuk

Dianne L Lacey

Rajabali Koduri

Abhishek Anil Sharma

Tahir Ghani

Anand S Murthy

Abhishek A Sharma

Rishabh Mehandru

Cory E Weber

Ibrahim Ban

Sagar Suthram

Leif R Paulson

Saurabh Lodha

Methods and apparatus to implement an integrated circuit to operate based on data access characteristics. For example, the integrated circuit comprises a first array comprising a first plurality of memory cells, a second array comprising a second plurality of memory cells, and both first and second arrays to store data of a processor. The second plurality of memory cells implements a selector transistor of a memory cell within using a thin-film transistor (TFT), and a memory control circuit is to write a first set of bits to the first array and a second set of bits to the second array upon determining the first set of bits is to be accessed more frequently than the second set of bits.

Embedded dynamic random-access memory (eDRAM) to operate based on data access characteristics

Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Integrated circuit structures having ultra-high conductivity global routing

In one embodiment, an integrated circuit package includes: a first die having a plurality of cores, each of the plurality of cores having a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM); and a second die comprising the DRAM, where at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die. Other embodiments are described and claimed.

Providing fine grain access to package memory

A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure has a dielectric layer comprised of an oxide of a first semiconductor material, wherein a second (and compositionally different) semiconductor material is formed between the dielectric layer and the first semiconductor material. In another embodiment, a portion of the second semiconductor material is replaced with a third semiconductor material in order to impart uniaxial strain to the lattice structure of the second semiconductor material.

Active regions with compatible dielectric layers

The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.

Ultra-abrupt semiconductor junction profile

Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, annealing the at least one contact area to form at least one silicide, and removing the unreacted first metal layer and second metal layer from the transistor structure and forming a conductive material in the at least one contact opening.

Method of forming CMOS transistors with dual-metal silicide formed through the contact openings

Methods and apparatus relating to a single silicon wafer having metal and alloy silicides are described. In one embodiment, two different silicides may be provided on the same wafer. Other embodiments are also disclosed.

Metal and alloy silicides on a single silicon wafer

Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a () plane to form at least one () region in the recessed source/drain region.

Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby

A CMOS device having dual-epi channels comprises a first epitaxial region formed on a substrate, a PMOS device formed on the first epitaxial region, a second epitaxial region formed on the substrate, wherein the second epitaxial region is formed from a different material than the first epitaxial region, an NMOS device formed on the second epitaxial region, and electrical contacts coupled to the PMOS and NMOS devices, wherein the electrical contacts are self-aligned.

CMOS device with dual-epi channels and self-aligned contacts

A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400&#xb0; C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures

The present invention describes a method of forming a highly doped polysilicon film. According to an embodiment of the present invention, a first silicon film is formed on a substrate. The first silicon film is then doped. Next, a second silicon film is formed on the doped first silicon film. The second silicon film is then doped.

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Hillsboro, OR, United States of America

Pushkar Ranade