Mie Fujitsu Semiconductor Limited

Suvolta, Inc.

Pushkar Ranade

Lucian Shifren

Scott E Thompson

Dalong Zhao

Thomas Hoffmann

Lance A Scudder

Teymur Bakhishev

Sachin R Sonkusale

Paul E Gregory

Michael Duane

Lingquan Wang

Weimin Zhang

Sameer S Pradhan

Charles Stager

Urupattur C Sridharan

U C Sridharan

Sung Hwan Kim

Yujie Liu

Reza Arghavani

Catherine De Villeneuve

Lance S Scudder

Bruce McWilliams

Toshifumi Mori

Taiji Ema

Kazushi Fujita

Mitsuaki Hori

Jing Wang

Junji Oh

Yasunobu Torii

Sachrin R Sonkusale

Uc Sridharan

Teymur Bakhisher

Ken-ichi Okabe

Toshiki Miyake

An advanced transistor with punch through suppression includes a gate with length Lg, a well doped to have a first concentration of a dopant, and a screening region positioned under the gate and having a second concentration of dopant. The second concentration of dopant may be greater than 5&#xd7;10dopant atoms per cm. At least one punch through suppression region is disposed under the gate between the screening region and the well. The punch through suppression region has a third concentration of a dopant intermediate between the first concentration and the second concentration of dopant. A bias voltage may be applied to the well region to adjust a threshold voltage of the transistor.

Advanced transistors with punch through suppression

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Semiconductor structure with multiple transistors having various threshold voltages

Semiconductor devices and methods of fabricating such devices are provided. The devices include source and drain regions on one conductivity type separated by a channel length and a gate structure. The devices also include a channel region of the one conductivity type formed in the device region between the source and drain regions and a screening region of another conductivity type formed below the channel region and between the source and drain regions. In operation, the channel region forms, in response to a bias voltage at the gate structure, a surface depletion region below the gate structure, a buried depletion region at an interface of the channel region and the screening region, and a buried channel region between the surface depletion region and the buried depletion region, where the buried depletion region is substantially located in channel region.

Buried channel deeply depleted channel transistor

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced &#x3c3;V(variation in V) compared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the Vsetting within a precise range. This Vset range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of Vsettings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control V(with a low &#x3c3;V) and V(the operating voltage supplied to the transistor), so that the body bias can be tuned separately from Vfor a given device.

Transistor with threshold voltage set notch and method of fabrication thereof

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced &#x3c3;Vcompared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The semiconductor structure includes an analog device and a digital device each having an epitaxial channel layer where a single gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the digital device and one of a double and triple gate oxidation layer is on the epitaxial channel layer of NMOS and PMOS transistor elements of the analog device.

Low power semiconductor transistor structure and method of fabrication thereof

A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

Reducing or eliminating pre-amorphization in transistor manufacture

A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.

CMOS gate stack structures and processes

A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced &#x3c3;Vcompared to conventional bulk CMOS and can allow the threshold voltage Vof FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the Vsetting within a precise range. This Vset range may be extended by appropriate selection of metals so that a very wide range of Vsettings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control V(with a low &#x3c3;V) and V, so that the body bias can be tuned separately from Vfor a given device.

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Los Gatos, CA, United States of America

Pushkar Ranade