United Microelectronics Corp.

Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Purakh Raj Verma

Kuo-Yuh Yang

Chia-Huei Lin

Sanford Chu

Guowei Zhang

Lap Chan

Shaoqiang Zhang

Shao-fu Sanford Chu

Ching-Yang Wen

Jia Zhen Zheng

Su Xing

Chu-Chun Chang

Guan Huei See

Jeoung Mo Koo

Chit Hwei Ng

Yisuo Li

Jian Xun Li

Li Wang

Rui Tze Toh

Yelehanka Ramachandramurthy Pradeep

Xingxing Chen

Manju Sarkar

Wen-Shen Li

Shyam Parthasarathy

Kai Cheng

Yemin Dong

Liang Yi

Ming Li

Chia-Liang Liao

Zeng Wang

Chee-Hau Ng

Yi Lu

Deyan Chen

Baofu Zhu

Dongli Wang

Chee Hau Ng

Johnny Chew

Jae Gon Lee

Pradeep Yelehanka

Shiang Yang Ong

Francis Lionel Benistant

Chih-Jung Wang

Kai Shao

Chao Jin

Ching-Pin Hsu

Bo Yu

Namchil Mun

Shajan Mathew

Yi Liang

Bo Tao

Kah-Wee Ang

Ramadas Nambatyathu

Choon Beng Sia

Wei Si

Zhiqing Li

Dong Yemin

Jian Xie

Chunlin Zhu

Hwee Ngoh Chua

Jia Zhen

Jinyu Liao

Dong Yin

Joe Jin Kuek

Xiao Yuan Zhi

Zhanfeng Liu

Shyue Seng Tan

Elgin Kiok Quek

Yung Fu Chong

Zhibiao Zhou

Chung Foong Tan

Lee Wee Teo

Da-Wei Lai

Zhao Lun

Chew Hoe Ang

Dong Kyun Sohn

Liang-Choo Hsia

Chunshan Yin

Yun Ling Tan

Sia Choon Beng

Hai Biao Yao

Wye Boon Loh

Runshun Wang

Ng Chit Hwei

Hong Yang

Kah Wee Ang

Liming Li

Kemao Lin

Ke Dong

Kun Liu

Beng Lye Oh

Yuzhan Wang

Chao Cheng

Zhen Jia Zheng

Han Xiao

Zhang Guowei

Cho Khon

Tao Jiang

Youzhou Hu

Wenli Liu

A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device wafer includes a first insulating layer, a first device layer on the first insulating layer, and a first bonding layer on the first device layer. The second device wafer includes a second insulating layer, a second device layer on a first side of the second insulating layer, and a second bonding layer on the second device layer. The second device layer includes a second device region and a second transistor in the second device region. The second device wafer is bonded to the first device wafer by bonding the second bonding layer with the first bonding layer. A shielding structure is on a second side of the second insulating layer opposite to the first side and vertically overlapped with the second device region.

Bonded semiconductor structure and method for forming the same

A method for fabricating an inductor module includes steps of: providing a substrate; forming a first inter-level dielectric layer on the substrate; forming a plurality of second inter-level dielectric layers on the first inter-level dielectric layer; forming a trench penetrating at least two of the second inter-level dielectric layers; and forming a first metal layer in the trench.

Method for fabricating inductor module

A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.

Semiconductor device and manufacturing method thereof

A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.

Method of forming protective layer utilized in silicon remove process

An integrated circuit device includes a substrate; an integrated circuit area disposed on the substrate and comprising a dielectric stack; a seal ring disposed in the dielectric stack and around a periphery of the integrated circuit area; a cap layer on the dielectric stack; a trench around the seal ring and exposing a sidewall of the dielectric stack; a memory storage structure disposed on the cap layer; and a moisture blocking layer continuously covering the integrated circuit area and the memory storage structure. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

Integrated circuit device

A method of fabricating an air gap includes receiving a first thickness information of an inter-metal dielectric layer formed on a substrate and receiving a second thickness information of an inter-layer dielectric layer formed on the substrate. Then, a first etching is performed, wherein the first etching includes etch the inter-metal dielectric layer based on a first etching control value corresponding to the first thickness information. After the first etching, a second etching is performed to etch the inter-layer dielectric layer based on a second etching control value corresponding to the second thickness information.

Method of fabricating an air gap

A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.

Multi-finger transistor structure and method of manufacturing the same

An integrated circuit device includes a substrate; an integrated circuit region on the substrate, said integrated circuit region comprising a dielectric stack; a seal ring disposed in said dielectric stack and around a periphery of the integrated circuit region; a trench around the seal ring and exposing a sidewall of the dielectric stack; and a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

Integrated circuit device and fabrication method thereof

A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.

Semiconductor structure with heat dissipation structure and method of fabricating the same

A method for fabricating an integrated circuit device is disclosed. A substrate is provided and an integrated circuit area is formed on the substrate. The integrated circuit area includes a dielectric stack. A seal ring is formed in the dielectric stack and around a periphery of the integrated circuit area. A trench is formed around the seal ring and exposing a sidewall of the dielectric stack. The trench is formed within a scribe line. A moisture blocking layer is formed on the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

Method for fabricating an integrated circuit device

A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.

Semiconductor structure and method of wafer bonding

A semiconductor structure includes following components. A first substrate has a first surface and a second surface opposite to each other. An HBT device is located on the first substrate and includes a collector, a base, and an emitter. A first interconnect structure is electrically connected to the base, located on the first surface, and extends to the second surface. A second interconnect structure is electrically connected to the emitter, located on the first surface, and extends to the second surface. A third interconnect structure is located on the second surface and electrically connected to the collector. An MOS transistor device is located on a second substrate and includes a gate, a first source and drain region, and a second source and drain region. Interconnect structures on the second substrate electrically connect the base to the first source and drain region and electrically connect the emitter to the gate.

Semiconductor structure and manufacturing method thereof

A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.

Parallel-connected trench capacitor structure with multiple electrode layers and method of fabricating the same

A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.

Semiconductor structure

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Singapore, Singapore

Purakh Raj Verma