Taiwan Semiconductor Manufacturing Comp. Ltd.

Pu-Fang Chen

Victor Y Lu

Shi-Chieh Lin

Yeur-Luen Tu

Cheng-Ta Wu

Shiang-Bau Wang

Yu-Hung Cheng

Ru-Liang Lee

Ting-Chun Wang

Yu-Lung Yeh

Sen-Hong Syue

Yen-Hsiu Chen

Po-Jung Chiang

I-Che Huang

Yueh-Chuan Lee

Chia-Chan Chen

Chih-Fu Chang

Shih-Hsien Huang

Yen Chuang

Bone-Fong Wu

Otto Chen

Fang-Chi Chien

Tung-Li Lee

Jih-Hwa Wang

Chung-chun Ho

Yi Jia Chen

Shao Hua Wang

An-Li Ho

Chi-En Huang

Cary Chia-Chung Lo

Wei-Zhe Chang

Shi-Jieh Lin

Tse-En Chang

Chieh Chih Ting

A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.

Structure for embedded gettering in a silicon on insulator wafer

Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.

Apparatus and methods for effective impurity gettering

Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the SOI structure thereof. In some embodiments, an impurity competing layer is formed on the dummy substrate. An insulation layer is formed over a support substrate. A front side of the dummy wafer is bonded to the insulation layer. An annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. Then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.

Fabrication method of metal-free SOI wafer

A method of manufacturing a semiconductor structure includes the following operations. A wafer includes a crystal orientation represented by a family of Miller indices comprising &#x3c;lmn&#x3e;, wherein l+m+n=1. A first chip and a second chip are over the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. A first included angle between the first direction and the crystal orientation is greater than or equal to 0 degree and less than 45 degrees.

Semiconductor structure and method for manufacturing the same

Structure and method for embedded gettering in a silicon on insulator wafer

A method of manufacturing a semiconductor structure includes the following operations. A wafer with an orientation mark at a first crystal orientation represented by a family of Miller indices comprising &#x3c;ijk&#x3e; is provided, wherein ijk=2. A first chip and a second chip are connected to a first surface of the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. The direction is not parallel to the first crystal orientation.

A method for forming a wafer supporting structure comprises growing a single crystal using a floating zone crystal growth process, forming a silicon ingot having an oxygen concentration equal to or less than 1 parts-per-million-atomic (ppma), slicing a wafer from the silicon ingot, cutting portions of the wafer to form a supporting structure through a mechanical lathe and applying a high temperature anneal process to the supporting structure.

Wafer supporting structure and method for forming the same

Present disclosure provides a method for manufacturing a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer, including providing the semiconductor wafer with a first dopant concentration of a dopant having a first conductivity type, forming a polysilicon layer over the front surface, removing the polysilicon layer from the front surface, and depositing the epitaxial layer at the front surface with a second dopant concentration of the dopant having the first conductivity type under a predetermined temperature. A transition width of the dopant having the first conductivity type across the semiconductor wafer and the epitaxial layer is controlled by the predetermined temperature to be at least about 0.75 micrometer. A semiconductor device and a semiconductor wafer with an epitaxial layer at a front surface of the semiconductor wafer are also disclosed.

Semiconductor substrate and manufacturing method of the same

In a method of manufacturing a semiconductor device, a thermal treatment is performed on a substrate, thereby forming a defect free layer in an upper layer of the substrate, where a remaining layer of the substrate is a bulk layer. A density of defects in the bulk layer is equal to or more than 1&#xd7;10cm, where the defects are bulk micro defects. An electronic device is formed over the defect free layer. An opening is formed in the defect free layer such that the opening does not reach the bulk layer. The opening is filled with a conductive material, thereby forming a via. The bulk layer is removed so that a bottom part of the via is exposed. A density of defects in the defect free layer is less than 100 cm.

Semiconductor device and manufacturing method thereof

Some embodiments relate to a silicon wafer having a disc-like silicon body. The wafer includes a central portion circumscribed by a circumferential edge region. A plurality of sampling locations, which are arranged in the circumferential edge region, have a plurality of wafer property values, respectively, which correspond to a wafer property. The plurality of wafer property values differ from one another according to a pre-determined statistical edge region profile.

Wafer strength by control of uniformity of edge bulk micro defects

A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.

Semiconductor structure and method

Semiconductor device having a through-silicon via and manufacturing method thereof

A method is provided for qualifying a semiconductor wafer for subsequent processing, such as thermal processing. A plurality of locations are defined about a periphery of the semiconductor wafer, and one or more properties, such as oxygen concentration and a density of bulk micro defects present, are measured at each of the plurality of locations. A statistical profile associated with the periphery of the semiconductor wafer is determined based on the one or more properties measured at the plurality of locations. The semiconductor wafer is subsequently thermally treated when the statistical profile falls within a predetermined range. The semiconductor wafer is rejected from subsequent processing when the statistical profile deviates from the predetermined range. As such, wafers prone to distortion, warpage, and breakage are rejected from subsequent thermal processing.

Method for qualifying a semiconductor wafer for subsequent processing

A system and method for mitigating annealing fingerprints in semiconductor wafers is provided. An embodiment comprises aligning the semiconductor wafers prior to each annealing step. This alignment generates similar or identical fingerprints in each of the semiconductor wafers manufactured. With the fingerprint known, a single compensation model for a subsequent photoresist may be utilized to compensate for the fingerprint in each of the semiconductor wafers.

Wafer alignment system and method

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Hsinchu, Taiwan

Pu-Fang Chen