Applied Materials, Inc.

National University of Singapore

Prayudi Lianto

Guan Huei See

Arvind Sundarrajan

Eric J Bergman

Prerna Sonthalia Goradia

Marvin L Bernt

Steven Verhaverbeke

Han-Wen Chen

John Lee Klocke

Sriskantharajah Thirunavukarasu

Yu Gu

Ranga Rao Arnepalli

Peng Suo

Mohamed Rafi

Pin Gian Gan

Andrivo Rusydi

Muhammad Avicenna Naradipa

Yin Wei Lim

Robert Jan Visser

John Leonard Sudijono

James S Papanu

Upendra V Ummethala

Kyuil Cho

Michael C Kutney

Giback Park

Glen T Mori

Vincent Dicaprio

Jie Zeng

Chintan Buch

Tapash Chakraborty

Karthik Elumalai

Charles Sharbono

Vicknesh Sahmuganathan

Sam Lee

Cheng Sun

El Mehdi Bazizi

Xundong Dai

Gaurav Mehta

Ramesh Chidambaram

Wei Ying Doreen Yong

Amulya Ligorio Athayde

Satwik Swarup Mishra

Khor Wui Cheng

Kuma Hsiung

Muhammad Azim

Peter Khai Mum Fung

Muhammad Azim Bin Syed Sulaiman

Ang Yu Xin Kristy

Sik Hin Chi

Shih-Chao Hung

Ricardo Fujii Vinluan

Nur Yasmeen Addina Mohamed Helmi Isik

Yi Kun Kelvin Goh

Alex Hung

Wei Hao Kew

Liu Jiang

Sachin Dangayach

Muhammad Adli Danish Bin Abdullah

ChangBum Yong

Rohith Cherikkallil

Mark McTaggart Wylie

Rahul Reddy Komatireddi

Sneha Rupa Kongara

Krishnaprasad Reddy Mallavaram

Remus Zhen Hui Koh

Si En Chan

A method and apparatus for training a learning model for automatic defect detection and classification of at least a portion of a processed wafer include receiving labeled images having defect classification types and features for portions of a post-processed wafer, creating a first training set comprising the received labeled images, training the machine learning model to automatically classify wafer portions based on at least one detected defect in respective wafer portions using the first training set, receiving labeled wafer profiles having respective downstream yield data, creating a second training set comprising the labeled wafer profiles and training the machine learning model, using the second training set, to automatically determine a respective downstream yield of a wafer based on a respective wafer profile. The machine learning model can be applied to at least one unlabeled wafer image to determine at least one defect classification for at least one portion of a wafer.

Defect classification of processed wafers

Methods and apparatus for processing a substrate are provided herein. For example, methods for enhancing surface hydrophilicity on a substrate comprise a) supplying, using a remote plasma source, water vapor plasma to a processing volume of a plasma processing chamber to treat a bonding surface of the substrate, b) supplying at least one of microwave power or RF power at a frequency from about 1 kHz to 10 GHz and a power from about 1 kW to 10 kW to the plasma processing chamber to maintain the water vapor plasma within the processing volume during operation, and c) continuing a) and b) until the bonding surface of the substrate has a hydrophilic contact angle of less than 10°.

Water vapor plasma to enhance surface hydrophilicity

A method of thinning a die engaged with a substrate is disclosed, utilizing dry etching of a top surface of the die with a plasma comprising fluorine to selectively remove the top surface of the die relative to a top surface of the substrate.

Silicon (Si) dry etch for die-to-wafer thinning

Methods and apparatus for processing a substrate are provided herein. For example, a method of processing a substrate using extended spectroscopic ellipsometry (ESE) includes directing a beam from an extended spectroscopic ellipsometer toward a surface of a substrate for determining in-situ ESE data therefrom during substrate processing, measuring a change of phase and amplitude in determined in-situ ESE data, and determining various aspects of the surface of the substrate using simultaneously complex dielectric function, optical conductivity, and electronic correlations from a measured change of phase and amplitude in the in-situ ESE data.

Methods and apparatus for processing a substrate

Methods and apparatus for processing a first substrate and a second substrate are provided herein. For example, a method of processing a substrate using extended spectroscopic ellipsometry (ESE) includes directing a beam from an extended spectroscopic ellipsometer toward a first surface of a first substrate and a second surface of a second substrate, which is different than the first substrate, determining in-situ ESE data from each of the first surface and the second surface during processing of the first substrate and the second substrate, measuring a change of phase and amplitude in determined in-situ ESE data, and determining one or more parameters of the first surface of the first substrate and the second surface of the second substrate using simultaneously complex dielectric function, optical conductivity, and electronic correlations from the measured change of phase and amplitude in the in-situ ESE data.

Embodiments of the present disclosure generally relate to planarization of surfaces on substrates and on layers formed on substrates. More specifically, embodiments of the present disclosure relate to planarization of surfaces on substrates for advanced packaging applications, such as surfaces of polymeric material layers. In one implementation, the method includes mechanically grinding a substrate surface against a polishing surface in the presence of a grinding slurry during a first polishing process to remove a portion of a material formed on the substrate; and then chemically mechanically polishing the substrate surface against the polishing surface in the presence of a polishing slurry during a second polishing process to reduce any roughness or unevenness caused by the first polishing process.

Planarization methods for packaging substrates

Exemplary methods of plating are described. The methods may include contacting a patterned substrate with a plating bath in a plating chamber. The patterned substrate includes at least one metal interconnect with a contact surface that is exposed to the plating bath. The metal interconnect is made of a first metal characterized by a first reduction potential. The methods further include plating a diffusion layer on the contact surface of the metal interconnect. The diffusion layer is made of a second metal characterized by a second reduction potential that is larger than the first reduction potential of the first metal in the metal interconnects. The plating bath also includes one or more ions of the second metal and a grain refining compound that reduces the formation of pinhole defects in the diffusion layer.

Diffusion layers in metal interconnects

A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.

Methods for forming alignment marks

Methods and apparatus for producing fine pitch patterning on a substrate. Warpage correction of the substrate is accomplished on a carrier or carrier-less substrate. A first warpage correction process is performed on the substrate by raising and holding a temperature of the substrate to a first temperature and cooling the carrier-less substrate to a second temperature. Further wafer level packaging processing is then performed such as forming vias in a polymer layer on the substrate. A second warpage correction process is then performed on the substrate by raising and holding a temperature of the substrate to a third temperature and cooling the substrate to a fourth temperature. With the warpage of the substrate reduced, a redistribution layer may be formed on the substrate with a 2/2 &#x3bc;m l/s fine pitch patterning.

Methods and apparatus for controlling warpage in wafer level packaging processes

Embodiments of methods for processing a semiconductor substrate are described herein. In some embodiments, a method of processing a semiconductor substrate includes removing material from a backside of a reconstituted substrate having a plurality of dies to expose at least one die of the plurality of dies; etching the backside of the reconstituted substrate to remove material from the exposed at least one die; and depositing a first layer of material on the backside of the reconstituted substrate and the exposed at least one die.

Methods of thinning silicon on epoxy mold compound for radio frequency (RF) applications

A method for producing an electrical component is disclosed using a molybdenum adhesion layer, connecting a polyimide substrate to a copper seed layer and copper plated attachment.

Method of fine redistribution interconnect formation for advanced packaging applications

Methods for bonding substrates used, for example, in substrate-level packaging, are provided herein. In some embodiments, a method for bonding substrates includes: performing electrochemical deposition (ECD) to deposit at least one material on each of a first substrate and a second substrate, performing chemical mechanical polishing (CMP) on the first substrate and the second substrate to form a bonding interface on each of the first substrate and the second substrate, positioning the first substrate on the second substrate so that the bonding interface on the first substrate aligns with the bonding interface on the second substrate, and bonding the first substrate to the second substrate using the bonding interface on the first substrate and the bonding interface on the second substrate.

Methods for bonding substrates

Methods and apparatus perform backside via reveal processes using a centralized control framework for multiple process tools. In some embodiments, a method for performing a backside via reveal process may include receiving process tool operational parameters from process tools involved in the backside via reveal process by a central controller, receiving sensor metrology data from at least one or more of the process tools involved in the backside via reveal process, and altering the backside reveal process based, at least in part, on the process tool operational parameters and the sensor metrology data by adjusting two or more of the process tools involved in the backside via reveal process. The profile parameters are configured to prevent backside via breakage during a chemical mechanical polishing (CMP) process.

Methods and apparatus for backside via reveal processing

A method of processing a substrate includes depositing a layer of uncured polymer material atop a substrate to cover an exposed conductive layer on the substrate, exposing at least one area of the layer using a photolithography process, developing the layer in the photolithography process to remove a first portion of uncured polymer material from the at least one area, etching the layer with a dry etch process to remove a second portion of uncured polymer material from the at least one area to expose a top surface of the conductive layer and form a via in the layer, and curing the layer to form a cured polymer material.

Methods for forming vias in polymer layers

A fan-out process using chemical mechanical planarization (CMP) reduces the step-height between a semiconductor die and the surrounding overmolding of a reconstituted wafer. The reconstituted wafer is formed by overmolding a back side of at least one die that is placed with an active side facing down. The reconstituted wafer is then oriented to expose the die and the active side. A polymer layer is then formed over the reconstituted wafer. A CMP process then removes a portion of the polymer layer until a certain thickness above the die surface is obtained, reducing the step-height between the polymer layer on top of the die surface and the polymer layer on the adjacent mold compound surface. The CMP process can also be performed after a subsequent redistribution layer is formed on the reconstituted wafer.

Methods and apparatus for semiconductor package processing

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Singapore, Singapore

Prayudi Lianto