Kepler Computing Inc.

Pratyush Pandey

Sasikanth Manipatruni

Amrita Mathuriya

Rajeev Kumar Dokania

Tanay Gosavi

Noriyuki Sato

Debo Olaosebikan

Niloy Mukherjee

Somilkumar J Rathi

Jason Y Wu

Ramamoorthy Ramesh

Mauricio Manfrini

Gabriel Antonio Paulius Velarde

Zeying Ren

Fnu Atiquzzaman

A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based memory devices

A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

Trench capacitors with continuous dielectric layer and methods of fabrication

Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications and methods of fabrication

Planar and trench capacitors for logic and memory applications and methods of fabrication

Planar and trench capacitors for logic and memory applications

Pocket flow for trench capacitors integrated with planar capacitors on a same substrate and method of fabrication

Planar and trench capacitors with hydrogen barrier dielectric for logic and memory applications

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures

Dual hydrogen barrier layer for trench capacitors integrated with low density film for logic structures and methods of fabrication

Method of fabricating a perovskite-material based planar capacitor using rapid thermal annealing (RTA) methodologies

Method of fabricating a perovskite-material based trench capacitor using rapid thermal annealing (RTA) methodologies

A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where 'n' is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

Manganese or scandium doped multi-element non-linear polar material gain memory bit-cell

Rapid thermal annealing (RTA) methodologies for integration of perovskite-material based trench capacitors

Method of forming stacked ferroelectric planar capacitors in a memory bit-cell

Non-linear polar material based memory bit-cell with multi-level storage by applying different voltage levels

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Kensington, CA, United States of America

Pratyush Pandey