National Semiconductor Corporation

Prasad Chaparala

Constantin Bulucea

Fu-Cheng Wang

Chih Sieh Teng

D Courtney Parker

Chin-Miin Shyu

William David French

Sandeep Raj Bahl

Donald M Archer

Jeng-Jiun Yang

Douglas Brisbin

Denis Finbarr O'Connell

Jonggook Kim

Barry O'Connell

Peter J Hopper

Vladislav Vashchenko

Philipp Lindorfer

Sergei Drizlikh

David Courtney Parker

Heather McCulloh

A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors ('IGFETs'), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (, and) utilize empty wells (, and) in achieving desired transistor characteristics. Other IGFETs (, and) utilize filled wells (, and) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Configuration and fabrication of semiconductor structure using empty and filled wells

An insulated-gate field-effect transistor (110, 114, or 122) is fabricated so that its gate dielectric layer (or) contains nitrogen having a vertical concentration profile specially tailored to prevent boron in the overlying gate electrode (or) from significantly penetrating through the gate dielectric layer into the underlying channel zone (or) while simultaneously avoiding the movement of nitrogen from the gate dielectric layer into the underlying semiconductor body. Damage which could otherwise result from undesired boron in the channel zone and from undesired nitrogen in the semiconductor body is substantially avoided.

Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile

A gate dielectric layer (, or) of an insulated-gate field-effect transistor (, or) contains nitrogen having a vertical concentration profile specially tailored to prevent boron in the overlying gate electrode (, or) from significantly penetrating through the gate dielectric layer into the underlying channel zone (, or) while simultaneously avoiding the movement of nitrogen from the gate dielectric layer into the underlying semiconductor body. Damage which could otherwise result from undesired boron in the channel zone and from undesired nitrogen in the semiconductor body is substantially avoided.

Fabrication of an insulated-gate field-effect transistor () entails separately introducing three body-material dopants, typically through an opening in a mask, into body material () of a semiconductor body so as to reach respective maximum dopant concentrations at three different vertical locations in the body material. A gate electrode () is subsequently defined after which a pair of source/drain zones (and), each having a main portion (M orM) and a more lightly doped lateral extension (E orE), are formed in the semiconductor body. An anneal is performed during or subsequent to introduction of semiconductor dopant that defines the source/drain zones. The body material is typically provided with at least one more heavily doped halo pocket portion (and) along the source/drain zones. The vertical dopant profile resulting from the body-material dopants alleviates punchthrough and reduces current leakage.

Fabrication of field-effect transistor with vertical body-material dopant profile tailored to alleviate punchthrough and reduce current leakage

At least one source/drain zone (or) of an enhancement-mode insulated-gate field-effect transistor (or) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (M,M,M, orM) and a more lightly doped lower portion (L,L,L, orL) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value Vwhen the channel length is at a value L, are at least 0.03 volt less than Vwhen the channel length is approximately 0.3 &#x3bc;m greater than L, and materially decrease with increasing channel length when the channel length is approximately 1.0 &#x3bc;m greater than L.

Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel length

Fabrication of complementary first and second insulated-gate field-effect transistors (orandor) from a semiconductor body entails separately introducing (i) three body-material dopants into the body material () for the first transistor so as to reach respective maximum dopant concentrations at three different locations in the first transistor's body material and (ii) two body-material dopants into the body material () for the second transistor so as to reach respective maximum dopant concentrations at two different locations in the second transistor's body material. Gate electrodes (orandor) are subsequently defined after which source/drain zones (orandor) are formed in the semiconductor body. The vertical dopant profiles resulting from the body-material dopants alleviate punchthrough and reduce current leakage.

Fabrication of complementary field-effect transistors with vertical body-material dopant profiles tailored to alleviate punchthrough and reduce current leakage

A number of modified lateral DMOS (LDMOS) transistor arrays are formed and tested to determine if a measured value, such as a series on-resistance, substrate current, breakdown voltage, and reliability, satisfies process alignment requirements. The modified LDMOS transistor arrays are similar to standard LDMOS transistor arrays such that the results of the modified LDMOS transistor arrays can be used to predict the results of the standard LDMOS transistor arrays.

Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays

Each of a pair of differently configured like-polarity insulated-gate field-effect transistors (orandor) in a semiconductor structure has a channel zone of semiconductor body material, a gate dielectric layer overlying the channel zone, and a gate electrode overlying the gate dielectric layer. For each transistor, the net dopant concentration of the body material reaches multiple local subsurface maxima below a channel surface depletion region and below largely all gate-electrode material overlying the channel zone. The transistors have source/drain zones (or) of opposite conductivity type to, and halo pocket portions of the same conductivity type as, the body material. One pocket portion (or) extends along both source/drain zones of one of the transistors. Another pocket portion (or) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.

Semiconductor structure in which like-polarity insulated-gate field-effect transistors have multiple vertical body dopant concentration maxima and different halo pocket characteristics

Each of a pair of like-polarity IGFETs (orandor) has a channel zone (or) situated in body material (). Short-channel effects are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (andorand) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &#x3bc;m deep into the body material but not more than 0.4 &#x3bc;m deep into the body material. A pocket portion (or) extends along both source drain zones of one of the IGFETs. A pocket portion (or) extends largely along only one of the source/drain zones of the other IGFET so that it is an asymmetrical device.

Structure and fabrication of field-effect transistor for alleviating short-channel effects

A MOS transistor is formed with a dual-layer silicon oxynitride (SiON) etch stop film that protects the transistor from plasma induced damage (PID) and hot carrier degradation, thereby improving the reliability of the transistors. The first SiON layer is formed with SiHat a first flow rate, and the second SiON layer is formed with SiHat a second higher flow rate.

MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation

Fabrication of two differently configured like-polarity insulated-gate field-effect transistors (orandor) entails introducing multiple body-material semiconductor dopants of the same conductivity type into a semiconductor body. Gate electrodes (or) are defined such that each body-material dopant reaches a maximum concentration below the channel surface depletion regions, below all gate-electrode material overlying the channel zones (or), and at a different depth than each other body-material dopant. The transistors are provided with source/drain zones (or) of opposite conductivity type to, and with halo pocket portions of the same conductivity type as, the body-material dopants. One pocket portion (or) extends along both source/drain zones of one of the transistors. Another pocket portion (or) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.

Fabrication of like-polarity insulated-gate field-effect transistors having multiple vertical body dopant concentration maxima and different halo pocket characteristics

A test methodology is provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. A resistor is formed on a region of dielectric isolation material formed in a semiconductor substrate. The MIM capacitor is formed over the resistor and separated therefrom by dielectric material. A metal thermometer, formed from the same material as the plates of the MIM capacitor, is placed above the resistor and in close proximity to the capacitor. High current is forced through the resistor, causing both the metal thermometer and the MIM capacitor to heat up along with the resistor. The change in resistance of the metal thermometer is monitored. Using the known temperature coefficient of resistance (TCR) for the metal used to form both the capacitor and the thermometer, changes in the measured resistance of the metal thermometer are converted to temperature.

Method for testing metal-insulator-metal capacitor structures under high temperature at wafer level

A test structure and a test methodology are provided for testing metal-insulator-metal (MIM) capacitor structures under high temperatures at the wafer level. The test structure includes a resistor formed on a region of dielectric isolation material formed in a semiconductor substrate. The MIM capacitor is formed over the resistor and separated therefrom by dielectric material. A metal thermometer, formed from the same material as the plates of the MIM capacitor, is placed above the resistor and in close proximity to the capacitor. High current is forced through the resistor, causing both the metal thermometer and the MIM capacitor to heat up along with the resistor. The change in resistance of the metal thermometer is monitored. Using the known temperature coeffecient of resistance (TCR) for the metal used to form both the capacitor and the thermometer, changes in the measured resistance of the metal thermometer are converted to temperature.

Method and structure for testing metal-insulator-metal capacitor structures under high temperature at wafer level

The source/drain zones (andorand) of a p-channel IGFET (or) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each source/drain zone contains a main portion (M,M,M, orM) and a more lightly doped lower portion (L,L,L, orL) underlying, and vertically continuous with, the main portion.

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Sunnyvale, CA, United States of America

Prasad Chaparala