Intel Corporation

Praneeth Kumar Akkinepally

Frank Truong

Dilan Seneviratne

Brandon C Marin

Robert Alan May

Rahul Jain

Jason M Gamba

Whitney Michael Bryks

Srinivas V Pietambaram

Rahul N Manepalli

Jeremy D Ecton

Andrew James Brown

Yosuke Kanaoka

Jesse Jones

Shivasubramanian Balasubramanian

Robert L Sankman

Kristof Darmawikarta

Sri Ranga Sai Boyapati

Yonggang Li

Hiroki Tanaka

Pramod Malatkar

Prithwish Chatterjee

Lauren Ashley Link

Richard J Harries

Kyle Yazzie

Srinivas Venkata Ramanuja Pietambaram

Jieying Kong

Shruti Rajeev Jaywant

Naga Sivakumar Yagnamurthy

Xuefei Wan

Chelsea M Groves

An integrated circuit (IC) package includes a package substrate, a first die over the package substrate, a stack of a first material and a second material over the first die, where the first material is between the first die and the second material and the second material includes an organic passivation material, interconnect structures including vias on the first die and extending through the first and second materials and conductive bumps on the second material, and a second die over the first die and connected to the first die via the interconnect structures, where a taper angle between an inner portion of a side wall of one of the vias and a plane parallel to a bottom opening of the one of the vias is less than or equal to 90 degrees.

Organic passivation for fine pitch architectures

Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

Embedded die microelectronic device with molded component

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a substrate layer having a surface, wherein the substrate layer includes a photo-imageable dielectric (PID) and an electroless catalyst; a first conductive trace having a first thickness on the surface of the substrate layer; and a second conductive trace having a second thickness on the surface of the substrate layer, wherein the first thickness is greater than the second thickness.

Microelectronic assemblies having conductive structures with different thicknesses

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a microelectronic component embedded in the package substrate, the microelectronic component including: a substrate having a surface, where the substrate includes a conductive pathway and a mold material region at the surface, where the mold material region includes a through-mold via (TMV) electrically coupled to the conductive pathway, and where the mold material region is at the second surface of the package substrate; and a die conductively coupled, at the second surface of the package substrate, to the package substrate and to the TMV of the microelectronic component.

Embedded multi-die interconnect bridge having a substrate with conductive pathways and a molded material region with through-mold vias

A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

Electronic device package including a capacitor

Embodiments are generally directed to dielectric film with pressure sensitive microcapsules of adhesion promoter. An embodiment of an apparatus includes a dielectric film, the dielectric film including a dielectric material layer; a layer of pressure sensitive microcapsules on a first side of the dielectric material layer, the microcapsules including an adhesion promoter; and a cover material on the layer of microcapsules. The pressure sensitive microcapsules are to rupture upon application of a certain rupture pressure.

Dielectric film with pressure sensitive microcapsules of adhesion promoter

An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

Package architecture utilizing photoimageable dielectric (PID) for reduced bump pitch

A system is disclosed, which comprises a component carrier having a first side, and a second side opposite the first side; and a light source to couple light into the carrier. In an example, the carrier is to propagate, through internal reflection, at least a portion the light to both the first and second sides of the carrier. The portion of light may be sufficient to release a first component and second component affixed to the first and second sides of the carrier via a first photosensitive layer and second photosensitive layer, respectively.

Dual side de-bonding in component carriers using photoablation

A substrate for an electronic device may include one or more interconnect pockets. Each of the interconnect pockets may be defined by a first pocket wall and a second pocket wall that may extend between the first pocket wall and the second exterior surface of the substrate. The second pocket wall may extend from the first pocket wall at a wall angle that is greater than or equal to 90 degrees. Individual interconnects may be located within respective individual ones of the interconnect pockets.

Electronic device including a substrate having interconnects

Disclosed embodiments include in-recess fabricated vertical capacitor cells, that can be assembled as close to the surface of a semiconductor package substrate as the first-level interconnect surface. The in-recess fabricated vertical capacitor cells are semiconductor package-integrated capacitors. Disclosed embodiments include laminated vertical capacitor cells where a plated through-hole is twice breached to form opposing capacitor plates. The breached, plated through-hole capacitors are semiconductor package-integrated capacitors.

Package-integrated vertical capacitors and methods of assembling same

Embedded multi-die interconnect bridge having a molded region with through-mold vias

Microelectronic devices including an embedded die substrate including a molded component formed on or over a surface of a laminated substrate that, provides a planar outer surface independent of the contour of the adjacent laminated substrate surface. The molded component may be formed over at least a portion of the embedded die. In other examples, the molded component and resulting planar outer surface may alternatively be on the backside of the substrate, away from the embedded die. The molded component may include an epoxy mold compound; and may be formed through processes including compression molding and transfer molding.

An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.

Growing community of inventors

Tempe, AZ, United States of America

Praneeth Kumar Akkinepally