Intel Corporation

Intel Ndtm US LLC

Sk Hynix Nand Product Solutions Corp.

Pranav Chava

Sagar Upadhyay

Aliasgar S Madraswala

Bhaskar Venkataramaiah

Shantanu R Rajwade

Tarek Ahmed Ameen Beshari

Binh Ngo

Soo-yong Park

Systems, apparatuses and methods may provide for technology that includes a charge pump and applies a program voltage from the charge pump to selected wordlines in the NAND memory. The technology may also conduct a discharge of the program voltage from the charge pump and maintain a connection between the selected wordlines and a pass voltage of the charge pump while the program voltage is being discharged. In one example, the connection between the selected wordlines and the pass voltage prevents the selected wordlines from floating.

Pump discharge sequence improvements in external power supply mode for pulse recovery phases in non-volatile memory

For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.

Smart prologue for nonvolatile memory program operation

Systems, apparatuses, and methods provide for technology that stores a sampled dynamic start voltage value based on a fast to program plane. A current multi-plane program operation is received corresponding to a current cell block and wordline pair associated with a current enabled plane of a plurality of enabled planes. A block list is scanned based on the current cell block and wordline pair. The block list includes a plurality of entries including a reference start voltage corresponding to a reference cell block and wordline pair associated with a reference enabled plane. Additionally, the reference start voltage is reused as a dynamic start voltage in response to finding a match between the current cell block and wordline pair as compared to the reference cell block and wordline pair. Such a match is performed only for a least enabled plane of the plurality of enabled planes.

Block list management for wordline start voltage

Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.

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Folsom, CA, United States of America

Pranav Chava