Intel Corporation

Pramod Malatkar

Kyle Yazzie

Robert L Sankman

Naga Sivakumar Yagnamurthy

Drew W Delaney

Richard J Harries

Shawna M Liff

John Stephen Guzek

Mathew J Manusharow

Nachiket R Raravikar

Sairam Agraharam

Ravi Kiran Nalla

Weng Hong Teh

Dilan Seneviratne

Chandra Mohan Jha

Shankar Devasenathipathy

Mohit Mamodia

Steven A Klein

Prasanna Raghavan

Venkata Suresh R Guthikonda

Xiao Lu

Rajesh Kumar Neerukatti

Aleksandar Aleksov

Feras Eid

Chia-Pin Chiu

Rahul N Manepalli

Vijay K Nair

Yoshihiro Tomita

Yonggang Li

Joshua Heppner

Je-Young Chang

Robert M Nickerson

Carl L Deppisch

Dingying David Xu

Rajendra C Dias

Paul J Diglio

Christopher D Combs

Kuang C Liu

Praneeth Kumar Akkinepally

Mark J Gallina

Kyle Jordan Arrington

John J Beatty

Purushotham Kaushik Muthur Srinath

Nicholas Holmberg

James Edward Neeb

Aravindha Antoniswamy

Hemanth K Dhavaleswarapu

Patrick Nardi

Arnab Choudhury

David C McCoy

Huiyang Fei

Leigh M Tribolet

John Harper

Kevin Y Lin

Daniel Chavez-Clemente

Jieping Zhang

Alexander W Huettis

Jesus Gerardo Reyes Schuldes

Frank P Prieto

Jiongxin Lu

Mohit Sood

Ravindranth V Mahajan

Vijay Subramania

Michael Gregory Drake

Santosh Sankarasubramanian

John L Harper

Xuefei Wan

Joseph Bautista

Techniques and mechanisms for promoting heat conduction in a packaged device using a heat spreader that is fabricated by a build-up process. In an embodiment, 3D printing of a heat spreader successively deposit layers of a thermal conductor material, where said layers variously extend each over a respective one or more IC dies. The heat spreader forms a flat top side, wherein a bottom side of the heat spreader extends over, and conforms at least partially to, different respective heights of various IC dies. In another embodiment, fabrication of a portion of the heat spreader comprises printing pore structures that contribute to a relatively low thermal conductivity of said portion. An average orientation of the oblong pores contributes to different respective thermal conduction properties for various directions of heat flow.

Printed heat spreader structures and methods of providing same

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

Varied ball ball-grid-array (BGA) packages

Disclosed herein are systems and methods for mechanical failure monitoring, detection, and classification in electronic assemblies. In some embodiments, a mechanical monitoring apparatus may include: a fixture to receive an electronic assembly; an acoustic sensor; and a computing device communicatively coupled to the acoustic sensor, wherein the acoustic sensor is to detect an acoustic emission waveform generated by a mechanical failure of the electronic assembly during testing.

Mechanical failure monitoring, detection, and classification in electronic assemblies

A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.

Die back side structures for warpage control

A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages

An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.

Electronic package that includes lamination layer

Disclosed herein are integrated circuit (IC) packages with an electronic component having a patterned protective material on a face, as well as related devices and methods. In some embodiments, a computing device may include: an integrated circuit (IC) package with an electronic component having a protective material on the back face of the electronic component, where the protective material is patterned to include an area on the back face of the electronic component that is not covered by the protective material; a circuit board, where the IC package is electrically coupled to the circuit board; and a heat spreader, where the heat spreader is secured to the circuit board and in thermal contact with the area on the back face of the electronic component that is not covered by the protective material.

Integrated circuit packages with patterned protective material

A membrane test for mechanical testing of wearable devices is described. A mechanical testing system includes an actuation mechanism including a clamp to hold a membrane including stretchable electronics over an opening in the actuation mechanism, wherein the actuation mechanism is to apply pressure to the membrane through the opening; and a testing logic to control the application and release of pressure on the membrane by the actuation mechanism.

Membrane test for mechanical testing of stretchable electronics

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.

Systems, methods, and apparatuses for implementing a thermal solution for 3D packaging

A thermal heat for integrated circuit die processing is described that includes a thermal barrier. In one example, the thermal head has a ceramic heater configured to carry an integrated circuit die, a metal base, and a thermal barrier between the heater and the base.

Thermal head with a thermal barrier for integrated circuit die processing

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces and a ground plane therein; a functional semiconductor die electrically interfaced to the electrical traces of the substrate layer; a heat pipe thermally interfaced to a top surface of the functional semiconductor die; one or more interposers of an organic dielectric material electrically connected to the ground plane of the substrate layer and electrically connected to the heat pipe; in which the one or more interposers form the electromagnetic shield to electrically shield the functional semiconductor die; and further in which the one or more interposers form the organic stiffener are to mechanically retain the substrate layer in a planer form. Other related embodiments are disclosed.

Systems, methods, and apparatuses for implementing an organic stiffener with an EMI shield for RF integration

An apparatus, comprising a first platform comprising a first working surface having a first non-planar portion; and a second platform comprising a second working surface having a second non-planar portion, wherein: the second working surface is opposite the first working surface, a distance between the first working surface and the second working surface is adjustable, the first non-planar portion comprises a first curved portion, and the second non-planar portion comprises a second curved portion opposite the first curved portion.

Constrained cure component attach process for improved IC package warpage control

A method of assembly comprising providing an assembly probe, the assembly probe having an end coupling face; providing a droplet of fluid on the end coupling face of the assembly probe; coupling an electronic component to the end coupling face of the assembly probe with the fluid droplet, the electronic component having a peripheral dimension equal to or less than 2 mm in each of length, width and height; placing the electronic component on a substrate with the assembly probe; decoupling the electronic component from the end coupling face of the assembly probe; and assembling the electronic component to the substrate.

Method of assembling an electronic component using a probe having a fluid thereon

Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.

Methods of forming trenches in packages structures and structures formed thereby

Electronic device shape configuration technology is disclosed. In an example, an electronic device substrate is provided that can comprise a top surface, and a bottom surface opposing the top surface. The top surface and/or the bottom surface can have a non-rectangular shaped perimeter. An electronic device die is also provided that can comprise a top surface, and a bottom surface opposing the top surface. The top surface and/or the bottom surface can have a non-rectangular shaped perimeter. In addition, an electronic device package is provided that can comprise a substrate having a top surface configured to receive a die and a bottom surface opposing the top surface. The package can also include a die having a top surface and a bottom surface opposing the top surface. The die can be coupled to the top surface of the substrate. The top surface and/or the bottom surface of either the substrate, or the die, or both can have a non-rectangular shaped perimeter.

Non-rectangular electronic device components

Growing community of inventors

Chandler, AZ, United States of America

Pramod Malatkar