International Business Machines Corporation

Prabhakar Goel

Maurice T McMahon

Thomas W Williams

Sumit Dasgupta

Design rules and test structure are used to implement machine designs to thereby obviate during testing the need for mechanical probing of the chip, multichip module, card or board at a higher level of package. The design rules and test structure also provide a means of restricting the size of logic partitions on large logical structures to facilitate test pattern generation. A test mechanism is available on every chip to be packaged to drive test data on all chip outputs and observe test data on all chip inputs, independent of the logic function performed by the chip. A control mechanism is also provided to allow a chip to either perform its intended function or to act as a testing mechanism during package test. It is intended that the test mechanism built into every chip will be used in place of mechanical probes to perform a chip-in-place test and interchip wiring test of the package. The intent of the design rules is to design chips such that each chip can be 'isolated' for testing purposes through the pins (or other contacts) of a higher level package containing such chips. It is also required that the 'Level Sensitive Scan Design' (LSSD) discipline, or rules, be followed for each chip and for the package clock distribution network. Further, the LSSD Rules which ensures the capability of scanning data into and out of the package SRLs (shift register latches) must be satisfied for the total package.

Method of electrically testing a packaging structure having N

Method of electrically testing a packaging structure having n

One of the significant features of the invention, as in U.S. Pat. No. 3,783,254, is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. These shift register latches in the invention as well as in the patent contain a pair of latches where one is a 'master' latch and another a 'slave'. The structure in the patent requires the 'master' and 'slave' latches to be part of the shift register for scan-in/scan-out. However, only the 'master' may be set with data from the logic system surrounding it while the 'slave' may only be set with data which previously resided in the related 'master' latch. Thus, in those logic organizations where only the 'master' latch output is required, the usefulness of the 'slave' latch is limited to scan-in/scan-out. In the shift register latch of the invention, the 'slave' latch must be set with the data that resided in the related 'master' latch during scan-in/scan-out. However, in logic systems requiring the use of only one latch of the shift register latch, both 'master' and 'slave' latches can perform independent of the other; that is, each latch may be set with data from the logic system without any influence from the other latch in the same shift register latch. Similarly, both 'master' and 'slave' may feed different sections of the logic surrounding it.

Level sensitive scan design (LSSD) system

A path oriented decision making test pattern generator is embodied in a logic chip test system for testing large-scale integrated circuits having many internal nodes inaccessible to the test probes of chip testing machines. For each designated possible chip fault, consisting of a stuck-high or stuck-low voltage at a node of the chip logic network, the generator provides a test pattern of signals to be applied to the input pins of each chip, so that the resulting signal at an output pin indicates whether the fault is present in the chip.

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Poughkeepsie, NY, United States of America

Prabhakar Goel