Xilinx, Inc.

Prabha Jairam

Himanshu J Verma

An on-chip stuck-at fault detector in an integrated circuit using a test circuit for critical path testing can include a sequence circuit having a first sequential circuit and a second sequential circuit to sensitize the critical path between a source sequential circuit and a destination sequential circuit, an analyzer circuit for capturing an output from the destination sequential circuit and comparing a signal between the destination sequential circuit and the analyzer circuit at predetermined clock cycles, and a controller for strobing the analyzer circuit at the predetermined clock cycles. The first sequence and second circuits can both be initialized to a zero mode (e.g., x=0 and y=0). Thus, no stuck-at faults are determined if the destination sequential circuit and an analyzer sequential circuit in the analyzer circuit have different values and a zero result is captured at a sticky-bit flip flop.

On-chip stuck-at fault detector and detection method

A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit includes a first sequential circuit coupled in series with a second sequential circuit. A circuit under test is coupled between a source sequential circuit and a destination sequential circuit to form a series. The source sequential circuit and the first sequential circuit are coupled to the test pattern generator to receive the test pattern. A comparison circuit is coupled to receive a first output from the destination sequential circuit and a second output from the second sequential circuit. The comparison circuit is configured to compare the first output with the second output to provide a signature output.

Integrated circuit internal test circuit and method of testing by using test pattern and signature generations therewith

Integrated circuit internal test circuit and method of testing therewith

A test circuit in an integrated circuit (or) is used for verifying a critical path of a circuit () under test. The test circuit can include a sequence generator () generating a data signal for the critical path, a source sequential circuit () for receiving the data signal coupled to an input of the critical path, a destination sequential circuit (or) for receiving an output of the critical path, and an analyzer circuit (or) for verification of timing of the critical path by measuring timing from the source sequential circuit to a clock enable pin () or a set/reset pin () of the destination sequential circuit. The test circuit can further include a controller circuit () for strobing a comparison circuit () in the analyzer circuit at a predetermined clock time. The integrated circuit can be part of an FPGA or FPGA fabric.

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Fremont, CA, United States of America

Prabha Jairam