Texas Instruments Corporation

Pr Chidambaram

Haowen Bu

Srinivasan Chakravarthi

Rajesh B Khamankar

Lindsey H Hall

Douglas Ticknor Grider

Robert Christopher Bowen

Greg Charles Baldwin

Brian Ashley Smith

A method () of forming a transistor () includes treating () at least some of a semiconductor substrate () with carbon and then forming () a gate structure () over the semiconductor substrate. A channel region () is thereby being defined within the semiconductor substrate () below the gate structure (). Source and drain regions () are then formed () within the semiconductor substrate () on opposing sides of the channel () with a phosphorus dopant.

Phosphorus activated NMOS using SiC process

A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

Nitrogen based implants for defect reduction in strained silicon

Drain extended MOS transistors () and fabrication methods () therefor are presented, in which a voltage drop region () is provided in a well () of a second conductivity type between a channel () of a first conductivity type and a drain () to inhibit channel hot carrier or direct tunneling degradation of the transistor gate dielectric () for high voltage operation. The voltage drop region () has more dopants of the first conductivity type and/or fewer dopants of the second conductivity type than does the well () so as to shift the high fields away from the transistor gate dielectric ().

Drain extended MOS transistors and methods for making the same

A method () of forming a transistor includes forming a gate structure () over a semiconductor body and forming recesses () substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown () in the recesses, followed by forming sidewall spacers () over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body () after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.

Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel

A method () of forming a transistor includes forming a gate structure () over a semiconductor body and forming recesses () substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown () in the recesses, followed by forming sidewall spacers () over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body () after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.

Drive current improvement from recessed SiGe incorporation close to gate

Methods () are presented for transistor fabrication, in which first and second sidewall spacers () are formed laterally outward from a gate structure (), after which a source/drain region () is implanted. The method () further comprises removing all or a portion of the second sidewall spacer () after implanting the source/drain region (), where the remaining sidewall spacer () is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.

Transistor fabrication methods using dual sidewall spacers

A method () of forming a transistor includes forming a gate structure () over a semiconductor body and forming recesses () substantially aligned to the gate structure in the semiconductor body. Amorphous silicon regions are then formed () in the recesses. The amorphous silicon regions are re-crystallized. Sidewall spacers are formed () over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body () after forming the sidewall spacers. The re-crystallized silicon regions formed in the recesses reside close to the transistor channel and serve to facilitate improved carrier mobility in NMOS type transistor devices.

Methods, systems and structures for forming improved transistors

According to one embodiment of the present invention, a method of forming a semiconductor device includes forming a gate stack on an outer surface of a semiconductor body. First and second sidewall bodies are formed on opposing sides of the gate stack. A first recess is formed in an outer surface of the gate stack, and a first dopant is implanted into the gate stack after the first recess is formed. The first dopant diffuses inwardly from the outer surface of the gate stack that defines the first recess. The first dopant diffuses toward an interface between the gate stack and the semiconductor body. The first recess increases the concentration of the first dopant at the interface.

System and method for improved dopant profiles in CMOS transistors

The present invention provides a system for limiting degradation of a first semiconductor structure () caused by an electric field (), generated from within the semiconductor substrate () by high voltage on a second semiconductor structure (). A semiconductor device () is adapted to reduce the effective magnitude of the field&#x2014;as realized at structure&#x2014;to some fractional component (), or to render the angle ()&#x2014;at which the field approaches the first structure through a first substrate region ()&#x2014;acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region () within the first substrate region.

Versatile system for limiting electric field degradation of semiconductor structures

A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

Forming a retrograde well in a transistor to enhance performance of the transistor

A method () of forming a transistor includes forming a gate structure () over a semiconductor body and forming recesses () using an isotropic etch using the gate structure as an etch mask. The isotropic etch forms a recess in the semiconductor body that extends laterally in the semiconductor body toward a channel portion of the semiconductor body underlying the gate structure. The method further includes epitaxially growing silicon () comprising stress-inducing species in the recesses. The source and drain regions are then implanted () in the semiconductor body on opposing sides of the gate structure.

Increased drive current by isotropic recess etch

Transistor fabrication methods () are presented in which shrinkable sidewall spacers () are formed () along sides of a transistor gate (), and a source/drain implant is performed () after forming the sidewall spacer (). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material () following the source/drain implant ().

Transistor fabrication methods using reduced width sidewall spacers

The present invention provides a system and method for processing low voltage threshold transistors on a semiconductor wafer. The method may include: forming core transistors with drains on the semiconductor wafer; forming low voltage threshold transistors with drains on the semiconductor wafer; forming input output transistors with drains on the semiconductor wafer; forming a spacing layer over the core, low voltage and input output transistors; forming a first photoresist mask layer over the low voltage transistors; doping the drains of the core and the input output transistors, wherein the doping is a medium doping; forming a second photoresist mask layer over the input output transistors; and doping the drains of the core and the low voltage threshold transistors, wherein the doping is a medium doping.

Growing community of inventors

Richardson, TX, United States of America

Pr Chidambaram