United Microelectronics Corp.

Tsinghua University

Po-Kang Yang

Cheng-Guo Chen

Ta-Kang Lo

Kun-Yuan Wu

Chiu-Sheng Ho

Tai-You Chen

Zong-Hong Lin

Shang-Jr Chen

Yun-Ting Jao

Yi-Yun Ke

Che-Min Chiu

A triboelectric nanogenerator structure is provided. The triboelectric nanogenerator structure is composed of an upper electrode layer, a lower triboelectric layer, a lower electrode layer and an electric connecting member. The upper electrode layer is composed of a hybrid gel. The lower triboelectric layer corresponding to the upper electrode layer has a first surface and a second surface, and the first surface faces toward the upper electrode layer. The lower electrode layer is disposed at the second surface. The electric connecting member connects the upper electrode layer to the lower electrode layer.

Triboelectric nanogenerator structure, sensing system and disinfecting system

A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

Method of fabricating tunneling transistor

Tunneling transistor and method of fabricating the same

First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.

Method for fabricating semiconductor device

Growing community of inventors

Taoyuan, Taiwan

Po-Kang Yang