Taiwan Semiconductor Manufacturing Comp. Ltd.

Po-Hsiung Leu

Ding-I Liu

Si-Wen Liao

Kai-Shiung Hsu

Chun-Li Lin

Yong-Hung Yang

Cheng-Tsung Wu

Wen-Long Lee

Chun-Sheng Wu

Geng-Shuoh Chang

Lan-Hai Wang

Yen-Chan Lo

Yi-Fang Lai

Chih-Wei Chiang

Yi-Fang Li

Jen-Chi Chang

Mao-Cheng Lin

Hsiang-Sheng Kung

Kuang-Cheng Wu

Jheng-Uei Hsieh

Shian-Huei Lin

Jui-Fu Hsu

Chin-Feng Sun

Po-Chang Chen

Po-Chi Wu

Yung-Jung Chang

Keith Kuang-Kuo Koai

Shin-Yeu Tsai

Jyh-Nan Lin

Chen-Peng Fan

Chia-Ming Yang

Li Shu Chen

Ming-Shiou Kuo

Buh-Kuan Fang

Huan-Chieh Chen

Chi-Ching Lo

Chia-Ming Tai

Chih-Chiang Chiu

Tsang-Yu Liu

Tzu-Chun Lin

Ho-Ta Chuang

Yl-Fang Li

Lan Hai Wang

Yun-Da Fan

Chin-Feng Lin

A coating apparatus for forming a coating film over a substrate includes a spin chuck for holding and rotating the substrate, a central coating nozzle over a central portion of the substrate, a plurality of first coating nozzles surrounding the central coating nozzle and spaced apart from the central coating nozzle by substantially a same first distance, and a plurality of second coating nozzles surrounding the central coating nozzle and spaced apart from the central coating nozzle by substantially a same second distance, wherein the second distance is greater than the first distance.

Coating apparatus and method of forming coating film

A plasma processing system and a method for controlling a plasma in semiconductor fabrication are provided. The system includes a remote plasma module configured to generate a plasma. The system further includes a compound mixing member configured to receive the plasma. The system also includes a processing chamber configured to receive the plasma from the compound mixing member for processing. In addition, the system includes a detection module configured to monitor the plasma in the compound mixing member.

Method for controlling plasma in semiconductor fabrication

A method includes a patterned hard mask layer formed over a substrate. The substrate is etched using the patterned hard mask layer to form a trench therein but leaving at least one elongated portion of the substrate inside the trench. A first isolation layer is formed over the patterned hard mask layer. The first isolation layer fills the trench and covers the at least one elongated portion of the substrate. A portion of the first isolation layer is removed to expose the at least one elongated portion of the substrate. The at least one elongated portion of the substrate is thereafter removed to form a first opening. A second isolation layer is formed over the first opening, the patterned hard mask layer, and the first isolation layer, the second isolation layer sealing the first opening to form an air gap.

Semiconductor device having a shallow trench isolation structure and methods of forming the same

A thermal chemical vapor deposition (CVD) system includes a bottom chamber, an upper chamber, a workpiece support, a heater and at least one shielding plate. The upper chamber is present over the bottom chamber. The upper chamber and the bottom chamber define a chamber space therebetween. The workpiece support is configured to support a workpiece in the chamber space. The heater is configured to apply heat to the workpiece. The shielding plate is configured to at least partially shield the bottom chamber from the heat.

Thermal chemical vapor deposition system and operating method thereof

A deposition device structure is provided. The deposition device structure includes a heater in a chamber. The deposition device structure also includes a shower head over the heater. The shower head includes holes extending from a top surface of the shower head to a bottom surface of the shower head. The bottom surface of the shower head faces the heater. The bottom surface of the shower head has a first section and a second section. The second section of the bottom surface is rougher than the first section of the bottom surface.

Deposition device structure

A showerhead is configured to be mounted inside a processing chamber and provide a processing gas onto a semiconductor wafer inside the processing chamber. The showerhead includes a supply plenum, a faceplate, and an electrode plate assembly. The faceplate is disposed at a side of the supply plenum. The electrode plate assembly is disposed between a gas source and the supply plenum. The electrode plate assembly includes a first plate having a unitary construction and having a plurality of first gas holes, and a second plate having a unitary construction and having a plurality of second gas holes. The second plate is located between the first plate and the supply plenum and separated from the first plate. The plurality of second gas holes are partially overlapped but misaligned with the plurality of first gas holes. A semiconductor apparatus having the same and a semiconductor process are also provided.

Showerhead, semicondcutor processing apparatus having the same and semiconductor process

Method and system for controlling plasma in semiconductor fabrication

The method for forming a semiconductor structure includes forming a protection layer having a first portion and a second portion over a substrate and forming a dummy gate layer over the first portion and the second portion of the protection layer. The method for forming a semiconductor structure further includes patterning the dummy gate layer to form a dummy gate structure over the first portion of the protection layer and forming a spacer on a sidewall of the dummy gate structure over a second portion of the protection layer. The method for forming a semiconductor structure further includes replacing the first portion of the protection layer and the dummy gate structure by a gate dielectric layer and a gate electrode layer. In addition, a thickness of the protection layer is greater than a thickness of the gate dielectric layer.

Semiconductor structure with protection layer

The present disclosure relates to an integrated chip having gate electrodes separated from an epitaxial source/drain region by gaps filled with a flowable dielectric material. In some embodiments, the integrated chip has an epitaxial source/drain region protruding outward from a substrate. A first gate structure, having a conductive gate electrode, is separated from the epitaxial source/drain region by a gap. A flowable dielectric material is disposed within the gap, and a pre-metal dielectric (PMD) layer is arranged above the flowable dielectric material. The PMD layer continuously extends between a sidewall of the first gate structure and a sidewall of a second gate structure, and has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode. A metal contact is electrically coupled to the conductive gate electrode and is disposed within an inter-level dielectric layer over the PMD layer and the first gate structure.

Gap fill self planarization on post EPI

The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.

Interlayer dielectric structure with high aspect ratio process (HARP)

An apparatus comprises a first gas inlet coupled between a first pipe and a reaction chamber, wherein the first pipe configured to carry process gases, a second gas inlet coupled between a second pipe and the reaction chamber, wherein the second pipe configured to carry a precursor material in a gaseous state and a heating device coupled to the second pipe and the second gas inlet, wherein the heating device keeps an ambient temperature of the second pipe and the second gas inlet above a boiling point of the precursor material.

Apparatus for dielectric deposition process

A plasma reactor includes an enclosure having a top and a bottom and defining a processing chamber. Inlets are formed in the enclosure for injecting process gas into the chamber. An outlet is formed in the enclosure for withdrawing gas from the chamber. A platform is positioned to support a wafer in the chamber above the bottom. A plurality of coils is positioned above the top of the chamber. Each coil is coupled to a radio frequency generator.

High density plasma reactor with multiple top coils

A method of forming a coating film over a substrate is provided. The method includes spinning the substrate. The method further includes providing a central coating liquid spray over a central portion of the substrate. The method also includes providing first coating liquid sprays over the substrate. The first coating liquid sprays surround the central coating liquid spray and are spaced apart from the central coating liquid spray by a same first distance.

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Lujhu, Taiwan

Po-Hsiung Leu