Northrop Grumman Systems Corporation

Northrop Grumman Space & Mission Systems Corporation

Trw Limited

Po-Hsin Liu

Ioulia Smorchkova

Carol Osaka Namba

Robert Coffie

Wayne Yoshida

Richard Lai

Michael Wojtowicz

Jennifer Wang

Weidong Liu

Xiaobing Mei

Jane Lee

Ben Heying

Boris Hikin

Linh Dang

Ronald Grundbacher

Dwight C Streit

Michael Edward Barsky

Yaochung Chen

Roger S Tsai

Ronald W Grundbacher

Michael D Lange

Sumiko L Poust

Mike Barsky

Rosie M Dia

Mike Wojtowicz

Rob Coffie

Ling-Shine Lee

Gerry Mei

Rich Lai

Yeong-Chang Choug

Denise L Leung

Kin L Tan

A method for fabricating a double-recess gate structure for an FET device that includes providing a semiconductor wafer having a plurality of semiconductor layers and depositing an EBL resist layer on the wafer. The method also includes patterning the EBL resist layer to form an opening in the EBL resist layer and performing a first wet etch to form a first recess in the wafer. The method further includes depositing a dielectric layer over the EBL resist layer and into the first recess and performing a dry etch to remove a portion of the dielectric layer in the first recess. The method also includes performing a second wet etch through the opening in the dielectric layer to form a second recess, and depositing a gate metal layer in the first and second recesses and in the opening in the EBL resist layer to form a gate terminal.

Self-aligned double gate recess for semiconductor field effect transistors

A method is provided for forming a gate contact for a compound semiconductor device. The gate contact is formed from a gate contact portion and a top or wing contact portion. The method allows for the tunablity of the size of the wing contact portion, while retaining the size of the gate contact portion based on a desired operational frequency. This is accomplished by providing for one or more additional conductive material processes on the wing contact portion to increase the cross-sectional area of the wing contact portion reducing the gate resistance, while maintaing the length of the gate contact portion to maintain the operating frequency of the device.

Method of forming a gate contact

A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

Method of forming a high electron mobility transistor hemt, utilizing self-aligned miniature field mitigating plate and protective dielectric layer

A semiconductor device includes a T-gate disposed between drain and source regions and above a barrier layer to form a Schottky contact to the channel layer. A first inactive field mitigating plate is disposed above a portion of the T-gate and a second active field plate is disposed above the barrier layer and in a vicinity of the T-gate.

High electron mobility transistor semiconductor device having field mitigating plate and fabrication method thereof

A method and apparatusfor detecting the height of non-flat and transparent substrates using one or more reflectorspatterned on the surface of the substrateand adjusting the position of the substrate in its holder based on measurement of the height of the reflectors in comparison to a calibration markeron the holder and using appropriate spacerswith appropriate thickness to adjust the placement of the substrate at various locations to place the greatest portion of the substrate in an optimal focal range of the lithography system.

Method and apparatus for detecting and adjusting substrate height

High electron mobility transistor having self-aligned miniature field mitigating plate on a protective dielectric layer

In a method of forming a semiconductor device on a semiconductor substrate (), a photoresist layer () is deposited on the semiconductor substrate; a window () is formed in the photoresist layer () by electron beam lithography; a conformal layer () is deposited on the photoresist layer () and in the window (); and substantially all of the conformal layer () is selectively removed from the photoresist layer () and a bottom portion of the window to form dielectric sidewalls () in the window ().

High electron mobility transistor semiconductor device and fabrication method thereof

A method of fabricating a T-gate HEMT with a club extension comprising the steps of: providing a substrate; providing a bi-layer resist on the substrate; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to a T-gate opening; exposing an area of the bi-layer resist to electron beam lithography where the area corresponds to the shape of the club extension wherein the area corresponding to the club extension is approximately 1 micron to an ohmic source side of a T-gate and approximately 0.5 microns forward from a front of the T-gate; developing out the bi-layer resist in the exposed area that corresponds to the T-gate opening; developing out the bi-layer resist in the exposed area that corresponds to the club extension; and forming the T-gate and club extension through a metallization process.

Club extension to a T-gate high electron mobility transistor

An InP high electron mobility transistor (HEMT) structure in which a gate metal stack includes an additional thin layer of a refractory metal, such as molybdenum (Mo) or platinum (Pt) at a junction between the gate metal stack and a Schottky barrier layer in the HEMT structure. The refractory metal layer reduces or eliminates long-term degradation of the Schottky junction between the gate metal and the barrier layer, thereby dramatically improving long-term reliability of InP HEMTs, but without sacrifice in HEMT performance, whether used as a discrete device or in an integrated circuit.

High electron mobility transistor (HEMT) structure with refractory gate metal

A process for improving the yield of semiconductors, such as high electron mobility transistors (HEMTs), which are susceptible to damage during conventional metal lift-off techniques. In accordance with an important aspect of the invention, damage to relatively fragile structures, such as submicron dimensioned structures on semiconductors are minimized by utilizing an adhesive tape to peel off undesired metal in close proximity to submicron dimension structures. By using an adhesive tape to peel off undesired metal, damage to submicron dimension structures is minimized thus improving the yield.

Method to separate a metal film from an insulating film in a semiconductor device using adhesive tape

A high power pseudomorphic (PM) AlGaAs/InGaAs high electron mobility transistor (HEMT) (26) with improved gain at 94 GHz. The transistor (26) includes an InGaAs quantum well (32) having a silicon planar doping layer (34) located at the bottom. A donor layer (36) comprises AlGaAs with a silicon planar doping layer (37). The resulting transistor (26) exhibits superior gain and noise characteristics that relatively high power levels when operating at 94 GHz. The transistor (26) is produced using an optimized growth process which involves growing the quantum well at a relatively low temperature and then raising the temperature to grow subsequent layers.

High power pseudomorphic gallium arsenide high electron mobility

Growing community of inventors

Anaheim, CA, United States of America

Po-Hsin Liu