Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

National Taiwan Normal University

Po-Hsien Cheng

Miin-Jang Chen

Tze-Liang Lee

Chung-Ting Ko

Zhen-Cheng Wu

Chi On Chui

Tai-Chun Huang

Jr-Hung Li

Tse-An Chen

Chun-Yi Chou

Wan-Chen Hsieh

Jr-Yu Chen

Chi-Wen Liu

Yu-tung Yin

Chi-On Chui

Chih-Hung Sun

Yu-Tung Yin

Tsung-Hsun Yu

Methods of forming vias for coupling source/drain regions to backside interconnect structures in semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a conductive feature adjacent a gate structure; a dielectric layer on the conductive feature and the gate structure; a metal via embedded in the dielectric layer; and a liner layer between and in contact with the metal via and the dielectric layer, the liner layer being boron nitride.

Semiconductor devices including backside power via and methods of forming the same

In a method of manufacturing a semiconductor device, a metal gate structure is formed and cut into two pieces of metal gate structures by forming a gate end spaces. A first liner layer is formed in the gate end space, and a sacrificial layer is formed on the first liner layer, and recessed. A second liner layer is formed over the recessed sacrificial layer, an air gap is formed by removing the recessed sacrificial layer; and a third liner layer is formed over the second liner layer.

Method of manufacturing semiconductor devices including forming an air gap based on removing a recessed sacrificial layer

A method includes forming a semiconductor fin over a substrate; forming first, second, and third gate structures crossing the semiconductor fin; forming first and second epitaxial source/drain structures on opposite sides of the first gate structure, and forming third and fourth source/drain epitaxial structures on opposite sides of the third gate structure; forming first gate spacers, second gate spacers, third gate spacers on opposite sidewalls of the first, second, and third gate structures, respectively; forming a first hard mask over the first, second, and third gate structures; patterning the first hard mask to form a first opening; etching a portion of the second gate structure and a portion of the semiconductor fin through the first opening to form a recess; and forming a dielectric layer in the recess, in which a dielectric constant of the dielectric layer is lower than a dielectric constant of silicon oxide.

Semiconductor device and method for forming the same

A method for forming a semiconductor device includes providing a base device having a top dielectric layer, forming a sacrificial layer on the top dielectric layer, and patterning the sacrificial layer to form openings. The method also includes depositing first protective dielectric layer and a low-K dielectric layer in the opening and performing planarization to form a first planarized structure including sacrificial regions and low k regions separated by a first protective layer. Next, top portions of the low-k dielectric layer are replaced with a second protective dielectric layer to form a second planarized structure that includes enclosed dielectric structures separated by sacrificial regions. The method further includes replacing the remaining portions of the sacrificial layer with a target metal interconnect material to form a third planarized structure that includes metal interconnect material disposed between enclosed dielectric structures.

Semiconductor device and method for manufacturing the same

Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Ferroelectric MFM inductor and related circuits

A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

Semiconductor device, FinFET device and methods of forming the same

A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.

Semiconductor device and manufacturing method thereof

A deposition apparatus and a method are provided. A method includes placing a substrate over a platform in a chamber of a deposition system. A precursor material is introduced into the chamber. A first gas curtain is generated in front of a first electromagnetic (EM) radiation source coupled to the chamber. A plasma is generated from the precursor material in the chamber, wherein the plasma comprises dissociated components of the precursor material. The plasma is subjected to a first EM radiation from the first EM radiation source. The first EM radiation further dissociates the precursor material. A layer is deposited over the substrate. The layer includes a reaction product of the dissociated components of the precursor material.

Deposition apparatus and method with EM radiation

A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.

A method includes forming a dummy gate structure over a wafer. Gate spacers are formed on either side of the dummy gate structure. The dummy gate structure is removed to form a gate trench between the gate spacers. A gate dielectric layer is formed in the gate trench. A gate electrode is formed over the gate dielectric layer. Forming the gate dielectric layer includes applying a first bias to the wafer. With the first bias turned on, first precursors are fed to the wafer. The first bias is turned off. After turning off the first bias, second precursors are fed to the wafer.

In an embodiment, a method of manufacturing a semiconductor device includes preparing a deposition processing chamber by flowing first precursors to form a dielectric coat along an inner sidewall of the deposition processing chamber and flowing a second precursor to form a hydrophobic layer over the dielectric coat. In addition one or more deposition cycles are performed. Next, the second precursor is flowed again to repair the hydrophobic layer.

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Taipei, Taiwan

Po-Hsien Cheng