Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Hewlett-packard Development Company, L.p.

Rdc Semiconductor Co., Ltd.

Po-Hsiang Huang

Fong-yuan Chang

Sheng-Hsiung Chen

Chin-Chou Liu

Fong-Yuan Chang

Lee-Chung Lu

Yi-Kan Cheng

Chun-Chen Chen

Li-Chun Tien

Chin-Her Chien

Jyun-Hao Chang

Chung-Hsing Wang

Ting-Wei Chiang

Chi-Yu Lu

Shao-Huan Wang

Hui Yu Lee

Cheng-Hung Yeh

Jyh Chwen Frank Lee

Chung-Te Lin

Kuo-Nan Yang

Hsiu-Wen Hsueh

Pin-Dai Sue

Yen-Hung Lin

Yu-Hao Chen

Ka Fai Chang

Hui-Zhong Zhuang

Meng-Sheng Chang

Sen-Bor Jan

Chii-Ping Chen

Wen-Sheh Huang

An-Jiao Fu

Chih-Hsin Ko

Jerry Chang Jui Kao

Ting Yu Chen

Hiranmay Biswas

Yen-Pin Chen

Hui-Yu Lee

Yi-Chuin Tsai

Chou-Kun Lin

Chien-Ju Chao

Chia-Ming Hsu

Chih-Lin Chen

Tzu-Hen Lin

Tai-Yu Cheng

Clement Hsingjen Wann

Chih-Liang Chen

Shao-Yu Chou

Chih-Hao Chen

Jung-Chan Yang

Jerry Chang-Jui Kao

Yi-Shin Chu

Keh-Jeng Chang

Chung-Min Fu

Meng-Kai Hsu

Yu-Hsiang Chen

Jen Hung Wang

XinYong Wang

Ya-Ching Tseng

Meng-Fu You

Ming-Fa Chen

Dian-Hau Chen

Shuo-Mao Chen

Cheng-Lin Huang

Xinyu Bao

Chih-Chien Chi

Yung-Chih Wang

Pei-Hsuan Lee

Zhen-Cheng Wu

Yu-Yu Chen

Su-Jen Sung

Yuh-Jier Mii

Lipen Yuan

Nai-Wei Liu

Ho Che Yu

Ting-Kui Chang

Ya-Chi Chou

Shun-Li Chen

Shu-Hui Su

Ni-Wan Fan

Chung-hsing Wang

Chia-En Huang

Cheng-Chieh Hsieh

Jr-Hung Li

Wen-Hao Cheng

William Wu Shen

Shun Li Chen

Chia-en Huang

Po-Yu Chen

Chi-Yeh Yu

Kuan-Wei Huang

Wan-Yu Lo

Chih-wei Chang

Pochun Wang

Chien-Ying Chen

Jiing-Feng Yang

Chi-Feng Lin

Jiun-In Guo

Kai-Ming Liu

Chau-Chin Su

Wei-Ren Wang

In one example aspect, the present disclosure is directed to a method. The method includes receiving a workpiece having a conductive feature over a semiconductor substrate, forming a sacrificial material layer over the conductive feature, removing first portions of the sacrificial material layer to form line trenches and to expose a top surface of the conductive feature in one of the line trenches; forming line features in the line trenches, removing second portions of the sacrificial material layer to form gaps between the line features, and forming dielectric features in the gaps, the dielectric features enclosing an air gap.

Devices with reduced capacitances

A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.

Semiconductor device including parallel configuration

A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.

SOIC chip architecture

A method according to the present disclosure includes receiving a workpiece that includes a first source/drain feature, a first dielectric layer over the first source/drain feature, and a source/drain contact disposed in the first dielectric layer and over the first source/drain feature. The method further includes depositing a second dielectric layer over the source/drain contact and the first dielectric layer, forming a source/drain contact via opening through the second dielectric layer to expose the source/drain contact, depositing a sacrificial plug in the source/drain contact via opening, depositing a third dielectric layer over the second dielectric layer and the sacrificial plug, forming a trench in the third dielectric layer to expose the sacrificial plug, removing the sacrificial plug to expose the source/drain contact via opening, and after the removing of the sacrificial plug, forming an integrated conductive feature into the trench and the exposed source/drain contact via opening.

Homogeneous source/drain contact structure

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.

Layout design for header cell in 3D integrated circuits

A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Info packages including thermal dissipation blocks

The present disclosure relates a method of forming an integrated chip. The method includes forming a first interconnect within a first inter-level dielectric (ILD) layer over a substrate, and forming a second ILD layer over the first ILD layer. The second ILD layer is patterned to form an interconnect opening that exposes the first interconnect. A blocking layer is formed onto the first interconnect. A barrier layer is formed within the interconnect opening and the blocking layer is removed to expose the first interconnect. A second interconnect is formed within the interconnect opening.

Barrier free interface between BEOL interconnects

An interconnect structure according to the present disclosure includes a first dielectric layer, a first conductive feature and a second conductive feature in the first dielectric layer, a first dielectric feature disposed directly on the first conductive feature; a first etch stop layer (ESL) disposed over the first dielectric layer and the second conductive feature, a first conductive layer disposed on and in contact with the first dielectric feature, a second ESL disposed over the first conductive layer, a second dielectric layer disposed directly on the first ESL and the second ESL, a first via extending through the second dielectric layer and the second ESL to contact with the first conductive feature, and a second via extending through the second dielectric layer and the first ESL to contact with the second conductive feature.

One-time-programmable device structure

A method of making a semiconductor device includes electrically connecting a component to a first side of a first fuse, wherein the first fuse is a first distance from the component. The method further includes electrically connecting the component to a first side of a second fuse, wherein the second fuse is a second distance from the component, and the second distance is different than the first distance. The method further includes electrically connecting a second side of the second fuse to a dummy vertical interconnect segment.

Semiconductor device having fuse array and method of making the same

A method for forming a semiconductor device structure is provided. The method includes removing a portion of a dielectric layer to form a trench in the dielectric layer. The method includes forming a barrier layer in the trench. The method includes forming a seed layer in the trench and over the barrier layer. The seed layer is doped with manganese. The method includes annealing the seed layer in a first process gas including a first hydrogen gas. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the seed layer to the barrier layer during the annealing of the seed layer in the first process gas.

Method for forming a semiconductor structure by diffusing manganese from a seed layer to a barrier layer

An IC device includes first through third rows of fin field-effect transistors (FinFETs), wherein the second row is between and adjacent to each of the first and third rows, the FinFETs of the first row are one of an n-type or p-type, the FinFETs of the second and third rows are the other of the n-type or p-type, the FinFETs of the first and third rows include a first total number of fins, and the FinFETs of the second row include a second total number of fins one greater or fewer than the first total number of fins.

Integrated circuit fin structure

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Integrated circuit device with improved layout

A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein the first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

Systems and methods of estimating thermal properties of semiconductor devices

Techniques for color change of Information elements (IEs) are described. In an example, a color of the IE and a color of a region of a virtual environment surrounding the IE may be compared. Based on the comparison, it may be determined whether the IE is distinguishable from the region of the virtual environment. Further, based on the determination, the color of the IE may be changed to facilitate distinguishability of the IE.

Color change of information elements

A method (of generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks, the layout diagram being stored on a non-transitory computer-readable medium) includes: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in a group of cut patterns which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.

Method and system for generating layout diagram including wiring arrangement

Growing community of inventors

Tainan, Taiwan

Po-Hsiang Huang