Taiwan Semiconductor Manufacturing Comp. Ltd.

Po-Chin Chang

Pinyen Lin

Li-Te S Lin

Ru-Gun Liu

Wei-Liang Lin

Yu-Tien Shen

Ya-Wen Yeh

Sung-Li Wang

Wei-Hao Wu

Yung-Sung Yen

Shuen-Shin Liang

Chia-Hung Chu

Shih-Chun Huang

Yuting Cheng

Lin-Yu Huang

Hung-Yi Huang

Tzu-Pei Chen

Chin-Hsiang Lin

Hung-Chang Sun

Ya Hui Chang

Zi-Wei Fang

Akira Mineji

Chiu-Hsiang Chen

Harry Chien

Ming-Huan Tsai

Sheng-Tsung Wang

Ken-Yu Chang

Wei-Yip Loh

Hsu-Kai Chang

Hong-Mao Lee

Chien Wen Lai

Kuan-Kan Hu

Chuan-Hui Shen

Tzu Pei Chen

Chih-Hao Wang

Chia-Hao Chang

Cheng-Chi Chuang

Liang-Yin Chen

Shin-Yi Yang

Chia-Cheng Chen

Kai-Chieh Yang

Chun-Hung Wu

Chia-Wei Su

Yi-Hsuan Hsiao

Shih-Ting Hung

Chien-Wen Lai

Chun-I Tsai

Yan-Ming Tsai

Chun-Hung Liao

Jung-Hao Chang

Kan-Ju Lin

Tsun-Jen Chan

Jhih-Rong Huang

Cheng-Wei Lian

Chih-Shiun Chou

Inez Fu

Shao-An Wang

Gloria Wu

Min-Chiang Chuang

Szu-Hsian Lee

A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.

Semiconductor device including stacked via contact and method for manufacturing the same

A semiconductor device includes a semiconductor structure, a conductive nitride feature, a third dielectric feature, and a conductive line feature. The semiconductor structure includes a substrate, two source/drain regions disposed in the substrate, a first dielectric feature disposed over the substrate, a gate structure disposed in the first dielectric feature and between the source/drain regions, a second dielectric feature disposed over the first dielectric feature, and a contact feature disposed in the second dielectric feature and being connected to at least one of the source/drain regions and the gate structure. The conductive nitride feature includes metal nitride or alloy nitride, is disposed in the second dielectric feature, and is connected to the contact feature. The third dielectric feature is disposed over the second dielectric feature. The conductive feature is disposed in the third dielectric feature and is connected to the conductive nitride feature opposite to the contact feature.

Semiconductor device including conductive nitride feature and method of making the semiconductor device

Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.

Conductive structure interconnects with downward projections

A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.

Semiconductor device with conductive liners over silicide structures and method of making the semiconductor device

A semiconductor device includes two source/drain features, a gate structure, a first contact plug, a second contact plug, a conductive line, and a nitride capping layer. The two source/drain features are laterally arranged to each other. The one or more channel layers connects the two source/drain features. The gate structure engages the one or more channel layers and interposes the two source/drain features. The first contact plug extends from above a first source/drain feature of the two source/drain features to the first source/drain feature. The second contact plug extends from below a second source/drain feature of the two source/drain features to the second source/drain feature. The conductive line is disposed underneath the second contact plug and electrically coupled to the second contact plug. The nitride capping layer is disposed between the second contact plug and the conductive line.

Semiconductor device and manufacturing method thereof

A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.

Gate to source drain interconnects

The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

Semiconductor devices with a nitrided capping layer

In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Method of manufacturing semiconductor devices using directional process

A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

Capping structures in semiconductor devices

The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.

Ion beam etching apparatus and method

A method for forming a semiconductor structure includes forming a gate structure on a substrate; depositing a first dielectric layer over the gate structure; depositing a second dielectric layer over the first dielectric layer and having a different density than the first dielectric layer; performing a first etching process on the first and second dielectric layers to form a trench; performing a second etching process on the first and second dielectric layers to modify the trench; filling a conductive material in the modified trench.

Semiconductor structure and method for manufacturing the same

A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

Reducing pattern loading in the etch-back of metal gate

A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact and a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The conductive via is over the source/drain contact. From a top view, the conductive via has two opposite long sides and two opposite short sides connecting the long sides, and the short sides are shorter than the long sides and more curved than the long sides.

Semiconductor device with elongated pattern

A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

Method of forming metal features

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Taichung, Taiwan

Po-Chin Chang