Taiwan Semiconductor Manufacturing Comp. Ltd.

Po-Chen Lai

Shin-Puu Jeng

Po-Yao Lin

Chin-Hua Wang

Shu-Shen Yeh

Ming-Chih Yew

Che-Chia Yang

Yu-Sheng Lin

Chia-Kuei Hsu

Li-Ling Liao

Tsung-Yen Lee

Chien-Sheng Chen

Chien Hung Chen

Kuang-Chun Lee

Chien-Hung Chen

Chien-Hung Zordius Chen

Yi-Hang Lin

Chun-Wei Chen

Chien-Shen Chen

Yu Chen Lee

Ping-Tai Chen

Yi Hang Lin

A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Multi-chip device and method of formation

A semiconductor device package is provided, including a substrate, a semiconductor device, a ring structure, a lid structure, and at least one adhesive member. The semiconductor device is disposed over the substrate. The ring structure is disposed over the substrate and surrounds the semiconductor device. The ring structure comprises a first ring part and a second ring part on opposite sides of the semiconductor device. A first gap is formed between the first ring part and the semiconductor device, a second gap is formed between the second ring part and the semiconductor device, and the first gap is smaller than the second gap. The lid structure is disposed over the ring structure and extends across the semiconductor device. The adhesive member is disposed in the first gap and configured to connect the lid structure and the first surface of the substrate.

Semiconductor device package with stress reduction design

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure and a second chip structure over the wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The chip package structure includes a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

Chip package structure with ring structure

A fan-out package includes at least one semiconductor die attached to an interposer structure. a molding compound die frame laterally surrounding the at least one semiconductor die and including a molding compound material, and at least one stress buffer structure located on the interposer structure and including a stress buffer material having a first Young's modulus. The molding compound die frame includes a molding compound material having a second Young's modulus that is greater than the first Young's modulus.

Semiconductor chip package having underfill material surrounding a fan-out package and contacting a stress buffer structure sidewall

A method of forming a semiconductor package structure is provided. The method includes disposing a first semiconductor device on an interposer substrate, disposing the interposer substrate on a carrier substrate, applying a thermal interface material on the first semiconductor device, and attaching a lid on the carrier substrate to cover the first semiconductor device. The interposer substrate is disposed between the carrier substrate and the first semiconductor device. The lid includes a lower surface having a first recess facing the first semiconductor device, and a portion of the thermal interface material is accommodated in the first recess.

Method for forming semiconductor package structure

A semiconductor package includes a die, a first conductive pattern, a second conductive pattern and first and second under-ball metallurgy (UBM) patterns. The first conductive pattern and the second conductive pattern are disposed below and electrically connected to the die, wherein the first conductive pattern has an ellipse-like shape, and the second conductive pattern has a circular shape. The first and second under-ball metallurgy (UBM) patterns correspond to the first and second conductive patterns, the first conductive pattern has a first length, the second conductive pattern has a second length, the first and second UBM patterns have a third length, wherein the first length is larger than the third length and the second length is smaller than the third length.

Semiconductor packages having conductive patterns of redistribution structure having ellipse-like shape

A semiconductor package may include a package substrate including a dummy via on a first side of the package substrate, an interposer module on a second side of the package substrate opposite the first side of the package substrate, and a stiffener ring on the second side of the package substrate and including an edge that is substantially aligned with the dummy via.

Semiconductor package including package substrate with dummy via and method of forming the same

A package assembly includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and attached to the package substrate. The package lid includes an outer lid including an outer lid material and including an outer lid plate portion. The package lid further includes an inner lid including an inner lid material different than the outer lid material and including an inner lid plate portion attached to a bottom surface of the outer lid plate portion.

Package assembly lid and methods for forming the same

A package assembly includes a package substrate, a package lid located on the package substrate and including a plate portion, an outer foot extending from the plate portion, and an inner foot having a height greater than or equal to a height of the outer foot, extending from the plate portion and including a first inner foot corner portion located inside a first corner of the outer foot, and an adhesive that adheres the outer foot to the package substrate and adheres the inner foot to the package substrate.

Package assembly including lid with additional stress mitigating feet and methods of making the same

Structures and formation methods of a chip package structure are provided. The chip package structure includes adjacent first and second semiconductor dies bonded over an interposer substrate. The chip package structure also includes an insulating layer formed over the interposer substrate. The insulating layer has a first portion surrounding the first and second semiconductor dies and a second portion extending between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, and between the interposer substrate and the first and second semiconductor dies. The lateral distance from the top end of the first sidewall to the top end of the second sidewall is greater than the lateral distance from the bottom end of the first sidewall to the bottom end of the second sidewall.

Semiconductor die with tapered sidewall in package

A semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.

Semiconductor device package having dummy dies

A semiconductor package includes a redistribution structure, a first conductive pillar and a second conductive pillar, and a semiconductor device. The redistribution structure has a first surface and a second surface opposite to the first surface. The first conductive pillar and the second conductive pillar are disposed on the first surface of the redistribution structure and electrically connected with the redistribution structure, wherein a maximum lateral dimension of the first conductive pillar is greater than a maximum lateral dimension of the second conductive pillar, and a topography variation of a top surface of the first conductive pillar is greater than a topography variation of a top surface of the second conductive pillar. The semiconductor device is disposed over the first surface of the redistribution structure, wherein the semiconductor device comprises a third conductive pillar and a fourth conductive pillar, the third conductive pillar is bonded to first conductive pillar through a first joint structure, and the fourth conductive pillar is bonded to second conductive pillar through a second joint structure.

Semiconductor package and method of forming the same

Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

Semiconductor devices and methods of manufacturing

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.

Semiconductor package with riveting structure between two rings and method for forming the same

A package structure is provided. The package structure includes a semiconductor die over a redistribution structure, bonding elements below the redistribution structure, and an underfill layer surrounding the bonding elements and the redistribution structure. The semiconductor die has a rectangular profile in a plan view. A pitch of the bonding elements is defined as the sum of a diameter of the bonding elements and a spacing between neighboring two of the bonding elements. A first circular area of the redistribution structure is entirely covered and in direct contact with the underfill layer. The center of the first circular area is aligned with a first corner of the rectangular profile of the semiconductor die. A diameter of the first circular area is greater than twice the pitch of the bonding elements.

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Hsinchu County, Taiwan

Po-Chen Lai