Taiwan Semiconductor Manufacturing Comp. Ltd.

Xerox Corporation

Palo Alto Research Center Inc.

TSMC Nanjing Company, Limited

Pinyen Lin

Li-Te S Lin

Han-Yu Lin

Peter M Gulvin

Fang-Wei Lee

Po-Chin Chang

Tze-Chung Lin

Yao Rong Wang

Lalit Keshav Mestha

John Richard Andrews

Joel A Kubby

Jun Ma

Yi-Chen Lo

Chansyun David Yang

Chieh-Min Cheng

Bradley James Gerner

Jung-Hao Chang

Ru-Gun Liu

Sung-Li Wang

David H Pan

Wei-Liang Lin

Kristine A German

Yi-Ruei Jhan

Yu-Tien Shen

Ya-Wen Yeh

Shuen-Shin Liang

Keng-Chu Lin

Yung-Sung Yen

Wei-Hao Wu

Tzer-Min Shen

Bryan R Dolan

Shih-Chun Huang

Akira Mineji

Chin-Hsiang Lin

Chia-Hung Chu

Hsu-Kai Chang

Chao-Hsien Huang

Naveen Chopra

Jingkuang Chen

Kathleen A Feinberg

Peter Michael Kazmaier

Chung-Liang Cheng

Pang-Yen Tsai

Huang-Lin Chao

Hung-Chang Sun

Ya Hui Chang

Zi-Wei Fang

Baomin Xu

Gwan-Sin Chang

Yi-Lun Chen

Chia-Shiung Tsai

David Allen Mantell

Liang-Bih Lin

Grazyna E Kmiecik-Lawrynowicz

Sheng-Chau Chen

Palghat Srinivas Ramesh

Chan-Lon Yang

Chung-Cheng Wu

Scott M Silence

Ming-Huan Tsai

Andrew Wayne Hays

Yeong-Jyh Lin

Chih-Kai Yang

Fu-Ting Yen

Kuan-Liang Liu

Chia-Hao Chang

Paul J McConville

Jason Mathew LeFevre

Anthony Salvatore Condello

Yuhua Tong

David Joseph Gervasi

Rina Carlini

Shin-Yi Yang

Paul Farrell Smith

Trevor James Snyder

Dale Robert Mashtare

Paul Joseph Gerroir

Roger N Ciccarelli

Grace T Brewington

Terrance Lee Stephens

Nancy Y Jia

Barry Daniel Reeves

Samir Kumar

Daniel M Bray

Yu-Rung Hsu

Christopher G Lynn

Chien-Wen Lai

Hung-Yi Huang

David M Skinner

Richard W Seyfried

Chun-Hung Liao

Chih-Ching Wang

Carol A Fox

Steven M Malachowski

Wei-Yen Woon

George Cunha Cardoso

Bernard A Kelly

Chun-Yu Chen

John G VanDusen

David Alan Vankouwenberg

The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.

Dry etching of semiconductor structures with fluorine-containing gases

The present disclosure provides a method for repairing a seam within a conformally deposited material. One or more seam repairing precursor sources may be delivered to seams or voids using a carrier at a super critical fluid phase. At the super critical fluid phase, the carrier has liquid like density and gas like high diffusion capability, therefore capable of delivering the repairing precursor sources to seams or voids under surfaces of a structure. In some embodiments, carbon dioxide or argon may be used as a carrier.

Methods for seam repair and semiconductor structure manufactured thereof

Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.

Conductive structure interconnects with downward projections

A method for fabricating a semiconductor arrangement includes performing a first etching of a semiconductive structure to expose a first portion of a sidewall of a first layer adjacent the semiconductive structure. The first etching forms a first protective layer on the first portion of the sidewall of the first layer, and the first protective layer is formed from a first accumulation of by-product material formed from an etchant of the first etching interacting with the semiconductive structure. The method includes performing a first flash to remove at least some of the first protective layer.

Semiconductor arrangement and method for making

A semiconductor device structure is provided. The semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

Semiconductor device structure with inner spacer layer

The present disclosure describes a method to form a semiconductor device with air inner spacers. The method includes forming a semiconductor structure on a first side of a substrate. The semiconductor structure includes a fin structure having multiple semiconductor layers on the substrate, an epitaxial structure on the substrate and in contact with the multiple semiconductor layers, a gate structure wrapped around the multiple semiconductor layers, and an inner spacer structure between the gate structure and the epitaxial structure. The method further includes removing a portion of the substrate from a second side of the substrate to expose the epitaxial structure and the inner spacer structure, forming an oxide layer on the epitaxial structure on the second side of the substrate, and removing a portion of the inner spacer structure to form an opening. The second side is opposite to the first side of the substrate.

Air inner spacers

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.

Contact structure for semiconductor device

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

Isolation structures of semiconductor devices

A method of fabricating a semiconductor structure and the semiconductor structure are disclosed. The method uses high flow rate of an etchant and an optimized scan pattern, so that the obtained semiconductor structure is a device upside-down bonded to the carrier wafer without any silicon remaining and is ready for subsequent lithography process for back via contact.

Method of fabricating a semiconductor structure and semiconductor structure obtained therefrom

A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.

Inner spacer formation in multi-gate transistors

In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.

Method of manufacturing semiconductor devices

The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.

Spacer structure for semiconductor device and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.

Gate all around (GAA) transistor structures having a plurality of semiconductor nanostructures

In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Method of manufacturing semiconductor devices using directional process

A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.

Method for FinFet fabrication and structure thereof

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Rochester, NY, United States of America

Pinyen Lin