Mosel Vitelic Corporation

Ping-Wei Lin

Ming-Kuan Kao

Jui-Ping Li

Yi-Fu Chung

Yi-Shin Chang

A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator

An irradiation process method for forming polysilicon layer is disclosed. The method includes firstly forming an alpha-silicon layer on substrate. Then the temperature of the UHV-CVD chamber is increased and the wafer is sent into the chamber. Gas is then intermittently conducted into the vacuum-chamber apparatus. While increasing the temperature of the vacuum-chamber apparatus, the whole throughput thus increases and the process-time for the polysilicon layer thus decreases. Finally, the electrical capacity thus increases by forming the polysilicon layer.

Method for forming a hemispherical-grain polysilicon

The present invention relates to a method for forming rugged polysilicon capacitance electrodes uses for dynamic random access memory processes is disclosed. The method is capable in reducing process time, enhancing yield, and saving production cost. Wherein, the process of the present invention comprises: firstly, a semiconductor wafer is delivered into a low pressure chemical vapor deposition (LPCVD) tube. Herein, a non-doped or doped amorphous silicon layer is deposited on the surface top of electrodes. A rugged polysilicon capacitance is formed on top of the non-doped or doped amorphous silicon layer by using the methods of rising temperature and decreasing pressure. Then, an ion implantation is applied and follows by a wafer cleaning procedure and an annealing process, wherein those procedures are accomplished after the removal of the wafer from LPCVD tube. During the annealing process, the non-doped or doped amorphous silicon layer is transformed into a polysilicon layer under a temperature roughly about 850.degree.C. In particularly, an in-situ phosphorous doped amorphous silicon can be deposited prior to the formation of non-doped amorphous silicon layer, and won't influence the stages that follow.

Method for forming rugged polysilicon capacitor

Method to prevent the formation of a thinner portion of insulating layer

The present invention provides a method for enlarging the surface area of hemi-spherical grains on the surface of a semiconductor chip. The hemi-spherical grain structure is formed by combining a poly-silicon layer with an underlying amorphous silicon layer. In processing, the two layers are etched with a corrosive solution that etches the amorphous silicon layer at a higher rate than it etches the poly-silicon layer. In this way, a ring-shaped slot forms at the bottom of each hemi-spherical grain thus increasing the total surface area of the hemi-spherical grain structure. Furthermore, surface area of the storage node is increased and the cell capacitor capacitance increases in excess of 15%.

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Chia-I, Taiwan

Ping-Wei Lin