Nan Ya Technology Corporation

Ping Cheng Hsu

Kuo-Chien Wu

Ming Cheng Chang

Hung Ming Tsai

Ying Cheng Chuang

Sheng Wei Yang

Yi-Nan Chen

Hsien-Wen Liu

Tzu-Ching Tsai

Jiann-Jong Wang

Shih-Fan Kuan

Yinan Chen

Li-Han Lu

A memory array and a method for preparing the memory are provided. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

Method for preparing memory array with contact enhancement cap

The present disclosure provides a dynamic random access memory (DRAM) array. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.

Memory array with contact enhancement cap and method for preparing the memory array

A method for preparing a semiconductor device structure includes forming a target layer over a semiconductor substrate, and forming a plurality of first mask patterns over the target layer. The method also includes forming a lining layer conformally covering the first mask patterns and the target layer. A first opening is formed over the lining layer and between the first mask patterns. The method further includes filling the first opening with a second mask pattern, and performing an etching process on the lining layer and the target layer using the first mask patterns and the second mask pattern as a mask such that a plurality of second openings are formed in the target layer.

Method for preparing semiconductor device structure with lining layer

A method for fabricating the semiconductor device includes providing a substrate, forming a bottom conductive plug on the substrate, forming a semiconductor layer on the bottom conductive plug, rounding a top surface of the semiconductor layer, turning the semiconductor layer into an intervening conductive layer, and forming a top conductive plug on the intervening conductive layer

Method for fabricating semiconductor device with intervening layer

A method of manufacturing a semiconductor memory device includes providing a substrate with a drain, a source and a gate structure disposed on the substrate between the drain and the source; forming a first inter-layer dielectric covering the substrate and the gate structure; forming a plug in the first inter-layer dielectric, with a first part contacting the source of the substrate. In the next step, a second part of the plug is exposed through the first inter-layer dielectric, and a storage node landing pad is formed on the exposed second part of the plug; a second inter-layer dielectric is formed on the first inter-layer dielectric, covering the storage node landing pad; a bit line is formed, connected to the substrate through the second inter-layer dielectric and the first inter-layer dielectric; a third inter-layer dielectric is formed on the bit line; and, a storage node is formed on the third inter-layer dielectric.

Method of manufacturing a semiconductor device with self-aligning landing pad

The present application relates to a semiconductor device with an intervening layer and a method for fabricating the semiconductor device with the intervening layer. The semiconductor device includes a substrate, a bottom conductive plug positioned on the substrate, an intervening conductive layer positioned on the bottom conductive plug, and a top conductive plug positioned on the intervening conductive layer. A top surface of the intervening conductive layer is non-planar.

Semiconductor device with intervening layer and method for fabricating the same

The present application discloses a method for fabricating a semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled. method includes providing an active interposer comprising a programmable unit; providing a first logic die and bonding a first side of the active interposer onto the first logic die; providing a first memory die comprising a storage unit; and bonding the first memory die onto a second side of the active interposer, wherein the second side of the active interposer is parallel to the first side of the active interposer.

Method for fabricating semiconductor device with active interposer

The present application discloses a method for fabricating a semiconductor device with liners. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, inwardly forming a trench on the first surface of the substrate, forming a plurality of liners positioned on side surfaces of the trench, forming a first insulating segment filling the trench, and removing part of the substrate from the second surface to expose the first insulating segment and the plurality of liners.

Method for fabricating a semiconductor device

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes an active interposer including a programmable unit, a first memory die positioned above the active interposer and including a storage unit, and a first logic die positioned below the active interposer. The active interposer, the first memory die, and the first logic die are electrically coupled.

Semiconductor device with active interposer and method for fabricating the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of conductive features positioned above the substrate, a plurality of landing pads positioned above the substrate, a coverage layer positioned above the substrate, and a plurality of capacitor structures positioned above the substrate. An angle between the axes of two adjacent landing pads is less than 180 degrees.

Semiconductor device with a plurality of landing pads and method for fabricating the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first conductive body, a second conductive body positioned separate from the first conductive body, a plurality of liners respectively correspondingly attached to a side surface of the first conductive body and a side surface of the second conductive body, and a first insulating segment positioned between the first conductive body and the second conductive body.

Semiconductor device and method for fabricating the same

A semiconductor memory device includes a substrate with a drain and a source; a gate structure, disposed on the substrate between the drain and the source; a first dielectric, disposed on the substrate, covering the gate structure; a second dielectric disposed on the first dielectric; a plug having a first part in the first dielectric and a second part in the second dielectric, wherein the first part is in contact with the source of the substrate; a storage node landing pad, covering the second part of the plug and covered by the second dielectric; a bit line disposed on the second dielectric and connected to the drain of the substrate; a third dielectric disposed on the bit line; and a storage node, disposed on the third dielectric, contacting the storage node landing pad through the second dielectric and the third dielectric.

Semiconductor device with self-aligning landing pad and method of manufacturing the same

The present disclosure provides a voltage circuit. The voltage circuit includes a first input signal-inverting circuit, a second input signal-inverting circuit, a first level-shifting circuit, a second level-shifting circuit, a first diode circuit and a second diode circuit. The first input signal-inverting circuit receives an input signal and outputs a first inverted signal. The second input signal-inverting circuit receives the first inverted signal and outputs a second inverted signal. The first level-shifting circuit determines a voltage level of a first output node in response to the first and second inverted signals. The second level-shifting circuit determines a voltage level of a second output node in response to the first and second inverted signals. The first diode circuit is connected between a first voltage-supplying node and the first output node. The second diode circuit is connected between a second voltage-supplying node and the second output node.

Voltage circuit and method of operating the same

A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a semiconductor layer, a first conductor, a second conductor and a fuse. The first conductor is disposed over the semiconductor layer. The second conductor is disposed over the first conductor. The fuse is disposed between the first conductor and the second conductor, wherein the fuse includes a conductive portion and a non-conductive portion surrounded by the conductive portion, the conductive portion is in contact with the first conductor and the second conductor, and the non-conductive portion is in contact with the second conductor.

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Taipei, Taiwan

Ping Cheng Hsu