Taiwan Semiconductor Manufacturing Comp. Ltd.

Pin-Shyne Chin

Hsun-Chih Tsao

Hung-Chih Tsai

Ming-Chang Hsieh

Chih-Chang Chen

Wen-Jye Yue

Ching-Kwun Huang

Hsien-Chih Peng

Hsien-Chin Peng

A method of forming a thin gate insulator layer comprises forming an active region surrounded by STI regions; forming a first insulator layer on the active device region; forming a patterned photoresist layer over the first insulator layer and a at least a portion of the STI regions; etching the first insulator layer to expose a portion of the active device region, wherein the photoresist layer substantially protects the STI regions during etching; forming a thin gate insulator layer on the exposed portion of the active device region, wherein said first insulator layer located on a remaining portion of said active device region is converted to a thicker second insulator layer; and forming a conductive gate structure overlying a first portion of the thin gate insulator layer while a second portion of the thin gate insulator layer not covered by the conductive gate structure is removed.

Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device

In accordance with the objectives of the invention a new method is provided for the creation of a layer of a Resistance Protective Oxide (RPO) layer. A layer of ONO is deposited that is to function as the layer of RPO. The deposited layer of ONO is patterned and wet etched, removing the upper or first layer of silicon dioxide. The patterned and etch upper of first layer of silicon dioxide is used as a hardmask to remove the central layer of silicon nitride applying a wet etch. A wet etch is then applied to remove the remaining lower of second layer of silicon dioxide, completing the patterning of the layer of RPO.

Resist protect oxide structure of sub-micron salicide process

The invention forms a 1T Static Random Access Memory (SRAM) with a low concentration cell node region and a higher concentration bit line region (e.g., second bit line region). The method of the invention forms a 1T Static Random Access Memory (SRAM) that uses a resist mask to block a high concentration implant into the cell node region, but allows the high concentration implant into the bit line region to form a second (high concentration) bit line. The invention's 1T SRAM, with the low concentration cell node, has reduced p-n junction leakage at the cell node and increase date retention time.

Low leakage one transistor static random access memory

A method to fabricate a 1T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.

Method to modify 0.25 &#x3bc;m 1T-RAM by extra resist protect oxide (RPO) blocking

A method of forming a thin silicon dioxide gate insulator layer for use in dual gate insulator device has been developed, featuring a process sequence that results in a reduction of the recessing and notching of surrounding STI regions, and a reduction of silicon damage and device leakage, when compared to counterparts fabricated without the use of this invention. An insulator layer is grown on, and removed via a wet etch procedure, from only the portion of the active device region to be used to accommodate the thin silicon dioxide gate insulator component of the dual gate insulator device. The photolithographic layout and photoresist shape used for removal of these portions of the insulator layer, protect the surrounding STI regions from the wet etch procedure, in addition to leaving insulator layer on portions of the active device region, allowing the underlying portions of the active device region to be protected during a dry etch procedure used to define a conductive gate structure on the thin silicon dioxide gate insulator layer. The thin silicon dioxide gate insulator layer is grown on the portion of active device region previously occupied by the portion of insulator layer removed via the wet etch procedure.

A method to fabricate a T-RAM device, comprising the following steps. A semiconductor substrate having an access transistor area and an exposed bottom plate within a capacitor area proximate the access transistor area is provided. A gate with an underlying gate dielectric layer within the access transistor area are formed. The gate and underlying gate dielectric layer having sidewall spacers formed over their respective exposed side walls. A top plate with an underlying capacitor layer over the bottom plate within the capacitor area are formed. The top plate and underlying capacitor layer having sidewall spacers formed over their respective exposed side walls. A patterned resist protect oxide (RPO) layer is formed over at least the drain of the structure not to be silicided. Metal silicide portions are formed over the structure not protected by the RPO layer.

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Hsinchu, Taiwan

Pin-Shyne Chin