Taiwan Semiconductor Manufacturing Comp. Ltd.

Pin-Nan Tseng

Chia-Shiung Tsai

Ping-Yin Liu

Chung-Kuang Lee

Yeur-Luen Tu

Xiaomeng Chen

Shyh-Chyi Wong

Jyh-Kang Ting

Chia Shiung Tsai

Pi-Chen Shieh

Chen-Hua Douglas Yu

Chue-San Yoo

Sung-Mu Hsu

Jung-hsien Hsu

Jau-Jey Wang

Jyh-Min Tsaur

Jiunn-Wen Weng

Chong-Shi Chen

A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.

Dual facing BSI image sensors with wafer level stacking

Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed.

Methods for hybrid wafer bonding integrated with CMOS processing

The present invention provides a structure and a method of electrically connecting wiring layers by forming a stacked plug interconnect. The first wiring layer is formed over a dielectric layer and a top barrier layer is formed over the top of the first wire layer. Next, first sidewall spacers preferably composed of titanium nitride and tungsten are formed on the first wire layer sidewalls. An inter metal dielectric layer is formed over the surface. A via is then etched exposing the first wiring layer. The first titanium nitride/tungsten spacers act as an etch stop for the via etch and also increase the contact area of the wiring layers. A tungsten plug with an outer TiN barrier layer is formed filling the via contacting the first wiring layer. On top of the tungsten plug, a second wiring layer is formed also having titanium nitride and tungsten sidewall spacers. The spacers also fill in the recesses in the TiN plug barrier layer and fill in dimples in the top of the tungsten plugs.

Multi-layer wiring structure having conductive sidewall etch stoppers and a stacked plug interconnect

This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics.

Layout pattern for improved MOS device matching

This invention relates to a method for protecting regions of a spin-on-glass(SOG) layer, which covers usable semiconductor dice, from dissolution damage during an etch step which removes SOG along the wafer edge. The endangered dice have portions which lie in the area affected by the edge rinse. Instead of performing the edge etching step immediately after the deposition of the SOG, the endangered dice are first selectively partially cured by exposure to ultraviolet radiation. This makes the SOG over these dice resistant to the SOG solvent used for the edge rinse. Up to ten percent of the total usable dice on the wafer can be salvaged by the method of this invention.

Selective partial curing of spin-on-glass by ultraviolet radiation to

A process for creating tungsten plugs, to fill high aspect ratio contact holes, has been developed. Narrow seams in the center of a tungsten plug, are protected from the tungsten RIE etch back process, thus avoiding the creation of larger seams or voids. This is accomplished by delaying the tungsten RIE etch back step until formation of an overlying interconnect metallization structure, which will protect the underlying tungsten plug, and seam, during the subsequent tungsten RIE etch back procedure.

Self-aligned tungsen etch back process to minimize seams in tungsten

Method of making a multi-layer wiring structure having conductive

A method is described for fabricating field effect transistors (FETs) having double silicide gate electrodes and interconnecting lines for CMOS circuits. The method reduces the IR voltage drops and RC time delay constants, and thereby improves circuit performance. The method consists of forming FETs having gate electrodes and interconnecting lines from a multilayer made up of a doped first polysilicon layer, a first silicide layer (WSi.sub.2), and a doped second polysilicon layer. After patterning the multilayer to form the gate electrodes, a titanium (Ti) metal is deposited and annealed to form a second silicide layer on the gate electrodes, and simultaneously forms self-aligned Ti silicide contacts on the source/drain areas. The latitude in overetching the contact openings in an insulating (PMD) layer to the gate electrodes extending over the field oxide area is increased, and the contact resistance (R.sub.c) is reduced because of the presence of the WSi.sub.2 below the contact openings, even if the Ti silicide is completely removed during the contact etching.

Method for fabricating double silicide gate electrode structures on

A process for forming aluminum interconnect structures has been developed, that concentrates on alleviating the effects of the poor step coverage of the interconnect metallization, that develops in areas where aluminum overlies tungsten filled contact holes. A high pressure treatment of the aluminum based metallization layer is performed at pressures in the range of 50 to 120 Mega-pascal, to improve the coverage of the aluminum based layer, specifically in seams or voids in the underlying tungsten plugs.

Profile improvement of a metal interconnect structure on a tungsten plug

A method for making metal interconnections and buried metal plug structures for multilevel interconnections on semiconductor integrated circuits was achieved. The method utilizes a single patterned photoresist layer for etching trenches in an insulating layer, while at the same time protecting the device contact areas in the contact openings from being etched, thereby reducing process complexity and manufacturing cost. After the trenches are formed, the patterned photoresist layer and the photoresist in the contact openings is removed by plasma ashing, and a metal layer is deposited and etched back or chem/mech polished to form concurrently the metal interconnections and the buried metal plug contacts. The surface of the metal interconnections is coplanar with the insulating surface, thereby allowing the process to be repeated several times to complete the necessary multilevel of metal wiring needed to wire-up the integrated circuits while maintaining a planar surface.

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Hsin-Chu, Taiwan

Pin-Nan Tseng