Taiwan Semiconductor Manufacturing Comp. Ltd.

Pili Huang

Kuo-Ching Huang

Chun-Yang Tsai

Chao-Yang Chen

Cheng-Jun Wu

Wen-Ting Chu

Kuo-Chi Tu

Mickey Hsieh

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnects arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnects. The bottom electrode includes a first material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. The bottom electrode is between the data storage layer and the substrate. A reactivity reducing layer includes a second material and has a second electronegativity that is greater than or equal to the first electronegativity. The second material contacts a lower surface of the bottom electrode that faces the substrate.

Bottom electrode structure in memory device

Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.

Wakeup-free ferroelectric memory device

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes one or more lower interconnect layers arranged within a dielectric structure over a substrate. A bottom electrode is disposed over one of the one or more lower interconnect layers. A lower surface of the bottom electrode includes a material having a first electronegativity. A data storage layer separates the bottom electrode from a top electrode. A reactivity reducing layer contacts the lower surface of the bottom electrode. The reactivity reducing layer has a second electronegativity that is greater than or equal to the first electronegativity.

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Hsin-Chu, Taiwan

Pili Huang