Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Pieter Vorenkamp

Neil Y Kim

Sumant Ranganathan

Klaas Bult

Frank Carr

Sam Ziqun Zhao

Chun-Ying Chen

Rezaur Rahman Khan

Xiangdong Chen

Kevin Kunzhong Hu

Sampath K V Karikalan

Tom W Kwan

Arnoldus Venes

Myles H Wakayama

Jeyhan Karaoguz

Rudy J Van De Plassche

Ning Li

Eric Bruce Blecker

Victor Chiu-Kit Fong

Chao Tang

David A Sobel

Agnes Woo

Siavash Fallahi

Ichiro Fujimori

Reinier Van Der Lee

James Y C Chang

Ralph A Duncan

David K Chin

Anil Tammineedi

John Perzow

Haideh Khorramabadi

InSun Van Loo

Christopher M Ward

Aaron W Buchwald

Edward Law

Andrew J Castellano

Monika Gupta

Ahmadreza Rofougaran

John S Walley

Oscar Ernesto Agazzi

Steven T Jaffe

Howard A Baumer

Kevin Tunghai Chan

Gottfried Ungerboeck

Peter R Kinget

Kevin Lee Miller

Michael Q Le

Keshab K Parhi

Christopher Michael Ward

Thinh Cat Nguyen

Hui Wang

Christian Lutkemeyer

Sam Komarapalayam Karikalan

Daniel J Marz

Sampath Komarapalayam Karikalan

Richard Stephen Prodan

Donald George McMullin

Jay Edward Ackerman

Russell Eliot Radke

Brian Sprague

Neal Andrew Kistler

Qiang Fu

Chung-Ying Chen

Sumant Rangnathan

Richard Nelson

Sampath Komarapalayam Velayudham Karikalan

Kevin Hu

Sampath Karikalan

David Chin

Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer. The circuit assembly further includes an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps and an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly.

Thin recon interposer package without TSV for fine input/output pitch fan-out

A 3-dimensional (3-D) magnetic core device includes a substrate, a first magnetic shell formed on the substrate, and a first group of conductive traces embedded in a first insulator layer formed on the first magnetic shell. A magnetic core plane is formed on the first insulator layer, and a second group of conductive traces are embedded in a second insulator layer formed on the magnetic core plane. A second magnetic shell is formed on the second insulator layer, and the first and second group of conductive traces are conductively coupled by using conductive vias.

Magnetic-core three-dimensional (3D) inductors and packaging integration

A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

Semiconductor interposer having a cavity for intra-interposer die

A system and method for controlling performance and/or power based on monitored performance characteristics. Various aspects of the present invention may comprise an integrated circuit comprising a first circuit module that receives electrical power. A second circuit module may monitor one or more performance characteristics of the first circuit module and/or the integrated circuit. A third circuit module may, for example, determine power control information based at least in part on the monitored performance characteristic(s). The power control information may be communicated to power supply circuitry to control various characteristics of the electrical power. Various aspects of the present invention may also comprise an integrated circuit comprising a first module that monitors at least one performance characteristic of a first electrical device. The integrated circuit may also comprise modules that determine power control information based on the monitored performance characteristic(s) and communicate such power control information to power supply circuitry.

Power control system with performance monitoring

There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

Semiconductor package with a bridge interposer

An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

Stacked packaging using reconstituted wafers

Power regulator circuitry that can provide a regulated power signal. The power regulator circuitry may include data processing circuitry configured to determine the regulated power signal to arbitrate power supply requirements of first and second powered devices according to power supply information associated with the first and second powered devices. The power regulator circuitry may also include output circuitry configured to output the regulated power signal to one or both of the first and second powered devices.

Power supply integrated circuit with feedback control

A system and method for controlling characteristics of supplied electrical power. Various aspects of the present invention may comprise an integrated circuit comprising a first circuit module that receives electrical power. The integrated circuit may comprise a second circuit module that monitors at least one characteristic of electrical power received by at least one of the first circuit module and the integrated circuit. The second circuit module may also communicate with a third circuit module regarding the monitored at least one characteristic. Various aspects of the present invention may comprise an integrated circuit comprising a first module that monitors at least one characteristic of electrical power received by a first electrical device that is external to the integrated circuit. The integrated circuit may also comprise a second module that communicates with a second electrical device, external to the integrated circuit, regarding the monitored at least one characteristic.

On-board power supply monitor and power control system

There are disclosed herein various implementations of a system-in-package with integrated socket. In one such implementation, the system-in-package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, an interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The interposer is configured to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors. In addition, a socket encloses the first and second active dies and the interposer, the socket being electrically coupled to at least one of the first active die, the second active die, and the interposer.

System-in-package with integrated socket

Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. The PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required. If the PSE finds the PD to be non-compatible, the PSE can prevent the application of power to that PD device, protecting the PD from possible damage.

Apparatus and method for multipoint detection in power-over-ethernet detection mode

An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball.

Semiconductor package with improved testability

An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.

Programmable interposer with conductive particles

There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer.

Semiconductor package with ultra-thin interposer without through-semiconductor vias

Growing community of inventors

Laguna Niguel, CA, United States of America

Pieter Vorenkamp