Stmicroelectronics Gmbh

Stmicroelectronics (crolles 2) Sas

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Stmicroelectronics S.a.

International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics S.r.l.

Commissariat a L'energie Atomique

Stmicroelectronics (rousset) Sas

Stmicroelectronics (grenoble 2) Sas

Soitec

Bell Semiconductor, LLC

Commissariat À L'énergie Atomique Et Aux Énergies Alternatives

Pierre Morin

Nicolas J Loubet

Yann Mignot

Qing Liu

Emmanuel Augendre

Sylvain Maitrejean

Denis Rideau

Olivier Nier

Ajey Poovannummoottil Jacob

Kangguo Cheng

Ruilong Xie

John H Zhang

Xiuyu Cai

Maud Vinet

Shay Reboh

Laurent Grenouillet

Jody Alan Fronheiser

Didier Dutartre

Raluca Tiron

Paola Zuliani

Michel Haond

Emmanuel Josse

Maxime Argoud

Jorge Regolini

Philippe Brun

David Barge

Elise Baylac

Bruce Bennett Doris

Ali Khakifirooz

Juntao Li

Xin Miao

Shogo Mochizuki

Hong He

Sanjay C Mehta

Su Chen Fan

Kisik Choi

Steven J Bentley

Muthumanickam Sankarapandian

Murat Kerem Akarvardar

Philippe Boivin

Frédéric Allibert

Laurent-Luc Chapelon

Francois Andrieu

Olivier Weber

Laurent Favennec

Remy Berthelon

Jason Cantone

Jean-Pierre Oddou

Olivier Hinsinger

Daniel Benoit

Sylvie M Mignot

Stephane Zoll

Franck Arnaud

Lucile Broussous

Joseph S Washington

David Moreau

David Galpin

Catherine Chaton

A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

Transistor comprising a channel placed under shear strain and fabrication process

An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

Chip containing an onboard non-volatile memory comprising a phase-change material

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Method to induce strain in finFET channels from an adjacent region

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Method to induce strain in 3-D microfabricated structures

A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

Semiconductor device with fin and related methods

Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Co-integration of tensile silicon and compressive silicon germanium

A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

Integrated tensile strained silicon NFET and compressive strained silicon-germanium PFET implemented in FinFET technology

The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.

A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.

Phase change memory

The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps:

Method of manufacturing a structure having one or several strained semiconducting zones that may for transistor channel regions

A memory cell includes a phase-change material. A via is connected to a transistor and an element for heating the phase-change material. A layer made of a material (which is one of electrically insulating or has an electric resistivity greater than 2.5&#xb7;10&#x3a9;&#xb7;m and which is sufficiently thin to be crossable by an electric current due to a tunnel-type effect) is positioned between the via and the heating element. Interfaces between the layer and materials in contact with surfaces of said layer form a thermal barrier.

Memory cell comprising a phase-change material

Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphization recrystallization then germanium condensation.

Method for fabricating a device with a tensile-strained NMOS transistor and a uniaxial compression strained PMOS transistor

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Pierre Morin