United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Pi-Hung Chuang

Wei-Hao Huang

Shao-Wei Wang

Shih-Wei Su

Hao Che Feng

Hung Jen Huang

Hsin Min Han

Ping Wei Huang

Ming Shu Chiu

Wen-Chin Lin

Jen-Chieh Lin

Sun-Hong Chen

Lee-Yuan Chen

Chi-Lune Huang

Tai-Lin Chen

The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

Method for fabricating fin structure for fin field effect transistor

The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.

Fin structure for fin field effect transistor and method for fabrication the same

A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.

Planarization method

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Changhua County, Taiwan

Pi-Hung Chuang