Lsi Logic Corporation

Other

Lsi Corporation

Philippe Schoenborn

Roger Patrick

Frank Bose

Kai Zhang

Yong-Bae Kim

Nicholas F Pasch

Masaichi Eda

Mark A Franklin

Rongxiang Hu

Wilbur G Catabay

Richard D Schinella

Keith K Chao

Shumay X Dou

Dilip Vijay

John Rongxiang Hu

Sungki O

Hiroaki Takikawa

Ana Ley

Sang-Yun Lee

Yongbae Kim

Harry Toda

Sarah Neuman

Sheldon Aronowitz

Wei-Jen Hsia

Alexander H Owens

Hong-Qiang Lu

Pamela Shiell Trammel

John Haywood

Kiran Kumar

Ting P Yen

Laique Khan

Frank A Bose

Ramit Bhandari

Tony Lo

Anh-Ha Tran

The present invention is directed to a method of identifying test devices having excessive leakage current and also includes computer program products that enable the same. The method obtaining background test data using a test routine to measure the leakage current for a set of test devices as a function of a parameter associated with device speed for the device under test. From the test data, a leakage threshold function is defined that correlates leakage current with the parameter associated with device speed. The test routine and the leakage threshold function are then input into an automated testing apparatus configured to execute the test on production or other devices. Devices are tested to determine leakage current over a range of parameter values associated with device speed. The devices are then screened using the leakage threshold function to determine the status of the device.

Method of using automated test equipment to screen for leakage inducing defects after calibration to intrinsic leakage

A process for removal of a photoresist mask used to etch openings in low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and for removing etch residues remaining from either the etching of the openings or removal of the resist mask, while inhibiting damage to the low k dielectric material comprises. The structure is exposed to a reducing plasma to remove a portion of the photoresist mask, and to remove a portion of the residues remaining from formation of the openings in the layer of low k dielectric material. The structure is then exposed to an oxidizing plasma to remove any remaining etch residues from the openings in the layer of low k dielectric material or removal of the resist mask.

Process for removal of photoresist mask used for making vias in low K carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask

A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Method of preventing resist poisoning in dual damascene structures

A carbon-doped hard mask includes a dielectric material containing carbon which is released from the hard mask during a metal etching process. The released carbon is deposited on and bonds to sidewalls of the metal structure during the metal etching process to passivate the sidewalls of the metal structure and prevent lateral etching of the sidewalls during the metal etching process. The released carbon also prevents accumulation of metal residue in open fields.

Carbon-doped hard mask and method of passivating structures during semiconductor device fabrication

The subject matter described herein involves an improved etch process for use in fabricating integrated circuits on semiconductor wafers. The selectivity of the etch process for silicon carbide versus silicon oxide, organo silica-glass or other low dielectric constant type material is enhanced by adding hydrogen (H2) or ammonia (NH3) or other hydrogen-containing gas to the etch chemistry.

High selectivity SiC etch in integrated circuit fabrication

PROCESS FOR REMOVAL OF PHOTORESIST MASK USED FOR MAKING VIAS IN LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL, AND FOR REMOVAL OF ETCH RESIDUES FROM FORMATION OF VIAS AND REMOVAL OF PHOTORESIST MASK

A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10&deg; and about 75&deg; as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.

Method of forming local oxidation with sloped silicon recess

Via poisoning of vias formed in low k carbon-containing silicon oxide dielectric material is suppressed by forming the via in a layer of such dielectric material with a smooth inwardly sloped sidewall. Such a sloped sidewall via can be etched in a low k dielectric layer by first forming a via resist mask over the upper surface of such a dielectric layer, then heat treating the mask sufficiently to deform the sidewall geometry of the resist mask to form a sloped sidewall on the opening or openings in the heat treated resist mask. The resulting erosion of such a resist mask, during a subsequent etch step to form the via in the low k dielectric material through such a sloped sidewall resist mask, imparts a tapered or sloped sidewall geometry to the via which is then formed in the underlying layer of low k dielectric material. In a preferred embodiment, when the via is cut through several layers of different types of dielectric material, the smoothness of the sloped sidewall of the resulting via is enhanced by adjusting the selectivity of the via etch to uniformly etch each of the layers of dielectric material at approximately the same rate.

Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning

A method for making a gate in an integrated circuit. A gate layer is formed on a substrate, and a blocking layer is formed on the gate layer. The blocking layer is masked with a photoresist layer, and the photoresist layer is developed to define an exposed gate area. The blocking layer is etched in the gate area to expose the gate layer in the gate area, and the photoresist layer is removed. A metal layer is formed on the blocking layer and on the gate layer in the gate area. The metal layer is selectively reacted with the gate layer in the gate area to form a hard mask over the gate layer in the gate area. The metal layer is removed from the blocking layer. The blocking layer is selectively etched without substantially etching the hard mask in the gate area, to expose the gate layer surrounding the gate area. The exposed gate layer is etched to define a gate in the gate area. The hard mask remains on the gate, and functions as an electrical contact to the gate.

Self aligned gate

A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus. The substrate is then solvent cleaned to remove etch residues and then annealed to degasify the low k dielectric material. The substrate is then RF cleaned and a thin layer of PVD titanium is then formed in the same chamber over the surfaces of the openings. CVD titanium nitride is then formed over the titanium in the same vacuum apparatus. The coated openings are then filled with aluminum, tungsten, or copper.

Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning

A low k carbon-doped silicon oxide dielectric material dual damascene structure is formed by improvements to a process wherein a first photoresist mask is used to form via openings through a first layer of low k carbon-doped silicon oxide dielectric material, followed by removal of the first photoresist mask; and wherein a second photoresist mask is subsequently used to form trenches in a second layer of low k carbon-doped silicon oxide dielectric material corresponding to a desired pattern of metal interconnects for an integrated circuit structure, followed by removal of the second photoresist mask. The improved process of the invention comprises: forming a first hard mask layer over an upper layer of low k carbon-doped silicon oxide dielectric material previously formed over an etch stop layer formed over a lower layer of low k carbon-doped silicon oxide dielectric material on an integrated circuit structure; forming a first photoresist mask having a pattern of via openings therein over the first hard mask layer; etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first hard mask; then removing the first photoresist mask; forming a second hard mask layer over the first hard mask; forming a second photoresist mask having a pattern of trench openings therein over the second hard mask layer; etching the second hard mask layer through the second photoresist resist mask to form a second hard mask having the pattern of trench openings replicated therein without etching the layers of low k carbon-doped silicon oxide dielectric material beneath the first and second hard masks; then removing the second photoresist mask; then using the first and second hard masks to respectively form the via openings in the lower layer of low k carbon-doped silicon oxide dielectric material and trench openings in the upper layer of low k carbon-doped silicon oxide dielectric material; whereby a pattern of via openings and a pattern of trench openings can be formed in layers of low k carbon-doped silicon oxide dielectric material without damage to the low k carbon-doped silicon oxide dielectric material during removal of the photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings.

Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure

An apparatus for producing a plasma suitable for semiconductor processing at pressures in the low millitorr range. The apparatus includes a vacuum chamber with a dielectric window, a generally planar coil disposed adjacent the window outside the chamber and coupled to an appropriate power source, and a plasma initiator disposed within the chamber. Once the plasma is initiated, the planar coil sustains the plasma by inductive power coupling. In one embodiment the plasma initiator is a secondary electrode disposed within the chamber and coupled to a second RF power source. In an alternative embodiment both the secondary electrode and a target pedestal are coupled to the secondary RF power source through a power splitter. In an alternative embodiment, the plasma initiator is used to ionize a portion of the process gas and provide a plasma that may then inductively couple with the planar coil. Initial ionization of the process gas may be achieved by use of an ultraviolet light source, an ultraviolet laser, a high voltage power source such as a tesla coil, or an electrical arc forming device such as a spark plug.

Plasma initiating assembly

A process for forming a photoresist mask over a patternable layer of an integrated circuit structure formed on a semiconductor substrate is described wherein the photoresist mask is initially formed with oversized lateral dimensions over a layer of patternable material of an integrated circuit on a semiconductor substrate. The oversized resist mask is then optionally measured in a vacuum apparatus to determine the size of the critical dimensions; then dry etched, preferably in the same vacuum apparatus, to reduce the size of the resist mask; then measured to determine the size of the critical dimensions (preferably again in the same vacuum apparatus); and then, if necessary, further dry etched to further reduce the size of the critical dimensions. The dry etching and subsequent measurement steps are repeated until the desired critical dimensions of the resist mask are reached. If the dry etching step should accidentally overetch the resist pattern, the structure can still be reworked by removing the resist mask and applying a fresh resist layer as in the prior art. After the correctly sized resist mask has been formed and determined by the cycle of dry etch and measurement steps, the underlying patternable layer can be etched through the photoresist mask, with a greatly reduced chance that the etched pattern in the underlying layer will have unsatisfactory dimensions.

Process for forming photoresist mask over integrated circuit structures

Growing community of inventors

San Jose, CA, United States of America

Philippe Schoenborn