International Business Machines Corporation

Philippe Coronel

Renzo Maccagnan

Jean Canteloup

Pascal Costaganna

Edith Lattard

Jean-Phillippe Vassilakis

Francois Leverd

David Cruau

Frederic Lebrun

Lars Heineck

Philippe Lacombe

Eric Mass

The method of the present invention applies to any semiconductor structure provided with polysilicon filled deep trenches formed in a silicon substrate coated by a Si3N4 pad layer both in the &ldquo;array&rdquo; and &ldquo;kerf&rdquo; areas. First, a photoresist mask is formed onto the structure and patterned to expose the deep trenches only in the &ldquo;array&rdquo; areas. Deep trenches are then anisotropically dry etched to create recesses having a determined depth. Next, the photoresist mask is removed only in the &ldquo;array&rdquo; areas. A step of anisotropic dry etching is now performed to extend said recesses down to the desired depth to create the shallow isolation trenches. The photoresist mask is totally removed. A layer of oxide (STI oxide) is conformally deposited by LPCVD onto the structure to fill said shallow isolation trenches in excess. The structure is planarized to create the STI oxide regions and expose deep trenches in the &ldquo;kerf&rdquo; areas. The polysilicon in these deep trenches is partially or totally removed by etching. Finally, the Si3N4 pad layer is eliminated, creating recesses that will be used as alignment marks for the subsequent photolithography steps. If the polysilicon is not etched, the above method will produce polysilicon bumps instead that can be used for the same purpose.

Method of forming STI oxide regions and alignment marks in a semiconductor structure with one masking step

Method and system for real-time in-situ interactive supervision of a step performed in a tool during semiconductor wafer fabrication process. The system includes a tool and the computer attached thereto, an end point detection controller, a database and a supervisor to supervise the whole wafer processing for that step. The controller is used to monitor a key process parameter of the step and is adapted to perform in-situ measurements. The database contains the evolution of said process parameter in normal operating conditions and in all the identified deviations. It further contains the history of the wafer until this step and a reference to the batch and process names for this step and the wafer identification number. At the end of the step, the important process parameters and any alert code are stored in the database to up-date the wafer history. This technique allows a total clusterized wafer fabrication process and prevents wafer rejection.

Method and system for semiconductor wafer fabrication process real-time in-situ interactive supervision

According to the disclosed method, there is provided a structure consisting of a silicon substrate coated with a bottom thin SiO2 layer, a doped polysilicon layer, a refractory metal layer and a top Si3N4 capping layer. Said refractory metal and doped polysilicon layers will form a polycide layer under subsequent thermal treatments. First, a sacrificial layer of a dielectric material such as oxynitride is deposited onto the structure. Oxynitride is impervious to UV radiation and has excellent conformal properties. Then, a layer of a photoresist material is deposited onto the structure and patterned to form a mask. Now the dielectric and top Si3N4 layers are anisotropically etched using the photoresist mask. The mask is stripped and the refractory metal and doped polysilicon layers are anisotropically dry etched down to the SiO2 layer using the patterned dielectric layer as an in-situ hard mask. A conformal layer of Si3N4 is deposited onto the structure, then anisotropically dry etched until the thin SiO2 layer is exposed to form the Si3N4 spacers. Diffusion regions are formed in the substrate by ion implantation. A layer of BPSG is deposited onto the structure and planarized. Contact holes are formed to expose said diffusion regions and filled with a metal to create borderless metal contacts therewith.

Method of fabricating a Si3N4/polycide structure using a dielectric sacrificial layer as a mask

A conventional initial deep trench structure consists of a patterned Si,N,pad layer coated silicon substrate with deep trenches formed therein. The trenches are partially filled with doped polysilicon (POLY1). A dielectric film is interposed between said polysilicon fill and the substrate to create the storage capacitor. A TEOS SiO,collar layer conformally coats the upper portion of the structure. Now, the TEOS SiO,is dry etched in a two-step process performed in the same RIE reactor. In the first step, the TEOS SiO,is etched at least 6 times faster than the Si,N,(stopping on the Si,N,pad layer). In the second step, the operating conditions ensure a partially isotropic dry etch, preferably with twice the power and 1.25 times the pressure, thus providing a vertical etch rate 6&times; the horizontal rate. As a result of this step, the upper part of the silicon substrate in the trench is exposed without damages. Next, N-type dopant is implanted in the upper portion of the silicon substrate to create a doped region. The trench is filled with a layer of doped polysilicon (POLY2) which is planarized by chemical-mechanical polishing down to approximately the Si,N,pad layer surface and finally recessed down to a depth level substantially coplanar with the silicon surface substrate to create a POLY2 stud. The buried strap is formed by the doped region and POLY2 stud. The above method presents significant advantages in terms of product reliability, throughput improvements and process flow simplification.

Method of forming buried straps in DRAMs

An improved method of forming the buried plate regions in deep trench capacitors used in DRAM memory semiconductor circuits in which the polymer used in the deep trench is etched down to the desired depth in a reactive ion etch tool using an O,/CF,chemistry. Since optical/interferometric etch end-point detection system can be used to monitor the etch back step in its totality, the quantity of the polymer remaining in deep trenches can be very accurately controlled, which in turn will produce a well controlled buried plate region during the out-diffusion step of the arsenic dopant contained in the arsenic doped silicon glass layer.

Method for buried plate formation in deep trench capacitors

According to the present invention, there is disclosed a method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches according to a planarization main step which is comprised of three processing steps. The starting structure (10) consists of a silicon substrate (11) coated by a patterned Si.sub.3 N.sub.4 layer (12) which delineates shallow trenches (20A, 20B) with a conformal layer (22) of TEOS SiO.sub.2 formed thereon. A planarizing medium, typically two superimposed photoresist layers (24.25) is formed onto the resulting structure to provide a substantially planar surface. At this stage of the fabrication, the structure is standard. Now, this planar surface is translated by a non selective two-steps plasma etching in the TEOS SiO.sub.2 layer (22). Next, should some photoresist material remain onto the structure it would be removed. Finally, a highly selective TEOS SiO.sub.2 /Si.sub.3 N.sub.4 RIE etching step is performed which stops on the Si.sub.3 N.sub.4 layer. The preferred chemistry is C.sub.4 F.sub.8 /Ar or C.sub.4 F.sub.8 /CO/Ar mixture. There is no longer the notion of process window because both the 'silicon polish' and 'Si.sub.3 N.sub.4 pad residuals' type of defects are eliminated. The present method offers significant advantages in terms of final test yield improvement, cost reduction and reproducibility.

Method for planarizing TEOS SiO.sub.2 filled shallow isolation trenches

In the manufacturing of 16 Mbit DRAM chips, the deep trench formation process in a silicon wafer by plasma etching is a very critical step when the etching gas includes 0.sub.2. As a result, the monitoring of the trench formation process and thus the etch end point determination is quite difficult. The disclosed monitoring method is based on zero order interferometry. The wafer is placed in a plasma etcher and a plasma is created. A large area of the wafer is illuminated through a view port by a radiation of a specified wavelength at a normal angle of incidence. The reflected light is collected then applied to a spectrometer to generate a primary signal S of the interferometric type. Next, this signal is applied in parallel to two filters. A low-pass filter produces a first secondary signal S1 that contains data related to the deposition rate and the redeposited layer thickness. A band-pass filter produces a second secondary signal S2 that contains data related to the trench etch rate and depth. The band-pass filter is centered around the fundamental frequency of the interferometry phenomenon. These filtered signals are monitored as standard and the trench formation parameters such as the SiO.sub.2 redeposited layer thickness and the trench depth are accurately measured in real time to allow an accurate determination of the etch end point. It is worthwhile to have the optical emission of the plasma viewed by another spectrometer to generate a second primary signal S* that is used to validate the parameter measurements.

Method for real-time in-situ monitoring of a trench formation process

Detecting the desired etch end point in the dry etching of a structure that includes a dielectric film formed onto a substrate down to a given thickness Ef. The structure is placed in the chamber of an etching equipment provided with a view-port. A light source illuminates a portion of the structure at a normal angle of incidence through the view-port. The light contains at least two specified wavelengths (L1, L2) whose value is greater than a minimum value equal to 4*N*e (wherein N is the index of refraction and e the thickness error of the dielectric). The reflected light is applied to spectrometers tuned to each specified wavelength, for converting the reflected light into interference signals that are processed and analyzed in a dedicated unit to generate primary signals (S1, S2). An analysis of the primary signals is performed after a predetermined delay. For each wavelength, a pre-selected extremum of the primary signal is detected and a predetermined number of extrema is counted. The counting stops when the last extremum just before Ef is reached. As a result, the distance D between the last extremum and the given thickness is now determined. The etch rate ER is also measured in-situ before the last extremum.

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Massy, France

Philippe Coronel