Intel Corporation

Philip Yashar

Gokul Malyavanatham

James S Clarke

Christopher J Jezewski

Sridhar Balakrishnan

Rohan N Akolkar

Flavio Griggio

Gopinath Trichy

Anthony V Mule

An integrated circuit includes: a front end of line (FEOL) circuit including a transistor; and a back end of line circuit above the FEOL circuit and including insulator material having an interconnect feature therein. The interconnect feature includes: a core including copper; a first layer between the insulator material and the core, the first layer being distinct from the core; a second layer between the first layer and the core, the second layer being distinct from the first layer and the core, the second layer including a first metal and a second metal different from the first metal; and a capping member on the core and the second layer, the capping member including the second metal. In an embodiment, the first metal and the second metal are part of a solid solution in the second layer. In an embodiment, the first metal is ruthenium and the second metal is cobalt.

Copper interconnect cladding

An embodiment includes an apparatus comprising: a transistor formed on a substrate; and a metal interconnect formed in a dielectric layer above the transistor, wherein: the interconnect comprises a copper layer and a barrier layer that separates the copper layer from the dielectric layer, and the barrier layer comprises tantalum and niobium. Other embodiments are described herein.

Low resistance interconnect

Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.

Barrier layers

Growing community of inventors

Portland, OR, United States of America

Philip Yashar