International Business Machines Corporation

Philip Raymond Germann

Gerald Keith Bartley

Darryl John Becker

Mark Owen Maxson

Andrew Benson Maki

Paul Eric Dahlen

John Michael Borkenhagen

William Paul Hovis

John Edward Sheets, Ii

Matthew Stephen Doyle

Mark James Jeanson

Trevor Joseph Timpane

David Paul Paulsen

Todd Alan Christensen

Dennis Martin Rickert

Richard Boyd Ericson

Carl-Otto Nilsen

A stub of a via formed in a printed circuit board is backdrilled to a predetermined depth. A capacitance probe is positioned within the via. Then the capacitance probe is used to obtain a test capacitance measurement. The test capacitance measurement is compared to a predetermined baseline capacitance measurement. Residual conductive plating material in the backdrilled stub causes the test capacitance measurement to exceed the predetermined baseline capacitance measurement. An indication is made that the predetermined baseline capacitance measurement has been exceeded.

Residual material detection in backdrilled stubs

A device uses donor circuit blocks in a donor integrated circuit to replace defective circuit blocks in a recipient integrated circuit and create a functional integrated circuit. The recipient integrated circuit has a first number of cores, the first number including a recipient core, and the recipient core having a recipient circuit block, a switching element, and a recipient communication point, the first number of cores connected by a data bus. The recipient core has an intended function. The donor integrated circuit has a second number of cores, the second number smaller than the first number. The second number includes a donor core having a donor communication point electrically connected to a donor circuit block, the donor circuit block having the intended function. The recipient connection point is electrically connected to the donor connection point and the switching element switched to disable the recipient circuit block in the recipient core.

Donor cores to improve integrated circuit yield

An integrated circuit (IC) stack device for thermal management is disclosed. The IC stack device can include a primary IC having a first set of cores with a ratio of first enabled cores and first disabled cores. The IC stack device can also have a supplementary IC interfaced with the primary IC, and having a second set of cores with a second ratio of second enabled cores and second disabled cores, with the second ratio being less than the first ratio. The integrated circuit stack device can also include a cooling element located such that the primary integrated circuit is between the cooling element and the supplementary integrated circuit. The cooling element can be designed to facilitate heat dissipation of the first and second enabled cores of the primary integrated circuit and the supplementary integrated circuit.

Intelligent chip placement within a three-dimensional chip stack

A semiconductor chip may include a die having one or more circuits. The semiconductor chip may include a plurality of die bumps, each having a first geometry, a first vertical profile, and a first volume. The die bumps may be coupled to the die and in electrical communication with the one or more circuits. The semiconductor device may include a plurality of test bumps each having a second geometry, a second vertical profile, and the first volume. The test bumps may be coupled to the die and in electrical communication with the one or more circuits. The first geometry and the second geometry may be adapted for the plurality of test bumps to make connection with a wafer probe to the test bumps without making a connection to any of the die bumps during a die test.

Interconnect solder bumps for die testing

Apparatus, method and program product detect an attempt to tamper with a microchip by determining that an electrical path comprising one or more connections and a metal plate attached to the backside of a microchip has become disconnected or otherwise altered. A tampering attempt may also be detected in response to the presence of an electrical path that should not be present, as may result from the microchip being incorrectly reconstituted. Actual and/or deceptive paths may be automatically selected and monitored to further confound a reverse engineering attempt.

Continuity check monitoring for microchip exploitation detection

A field-effect transistor has a gate, a source, and a drain. The gate has a via extending through a semiconductor chip substrate from one surface to an opposite surface of the semiconductor chip substrate. The source has a first toroid of ion dopants implanted in the semiconductor chip substrate surrounding one end of the via on the one surface of the semiconductor chip substrate. The drain has a second toroid of ion dopants implanted in the semiconductor chip substrate surrounding an opposite end of the via on the opposite surface of the semiconductor chip substrate.

Field-effect transistor and method of creating same

A method, apparatus, and structure are provided for implementing selective rework for chip stacks. A backside metal layer to create resistive heating is added to a chip backside in a chip stack. A rework tool applies a predefined current to the backside metal layer to reflow solder connections and enables separating selected chips in the chip stack.

Implementing selective rework for chip stacks and silicon carrier assemblies

A method and system are provided for implementing enhanced memory performance management with configurable bandwidth versus power usage in a chip stack of memory chips. A chip stack of memory chips is connected in a predefined density to allow a predefined high bandwidth connection between each chip in the stack, such as with through silicon via (TSV) interconnections. Large-bandwidth data transfers are enabled from the memory chip stack by trading off increased power usage for memory performance on a temporary basis.

Implementing memory interface with configurable bandwidth

A method and structures are provided for implementing semiconductor signal-capable capacitors with deep trench and Through-Silicon-Via (TSV) technologies. A deep trench N-well structure is formed and an implant is provided in the deep trench N-well structure with a TSV formed in a semiconductor chip. At least one angled implant is created around the TSV in a semiconductor chip. The TSV is surrounded with a dielectric layer and filled with a conducting material which forms one electrode of the capacitor. A connection is made to one implant forming a second electrode to the capacitor.

Implementing semiconductor signal-capable capacitors with deep trench and TSV technologies

Method and apparatus for optimally placing memory devices within a computer system. A memory controller may include circuitry configured to retrieve or one or more performance metrics a plurality of memory devices connected thereto. Based on the performance metrics and one or more predefined rules for placing memory devices, the circuitry may determine an optimal placement of the memory devices in the system.

Sorting movable memory hierarchies in a computer system

A method and apparatus are provided for implementing interleaved-dielectric joining of multi-layer laminates. First and second multi-layer laminates are provided, each having with a laminated portion and an unlaminated portion. The first and second multi-layer laminates are joined together at the unlaminated portions by interleaving a plurality of dielectric layers of the first and second multi-layer laminates. Respective conductors carried by adjacent dielectric layers are connected. The interleaved unlaminated portions are laminated together with heat and pressure, to create a larger laminate of the joined first and second multi-layer laminates.

Growing community of inventors

Oronoco, MN, United States of America

Philip Raymond Germann