Adeia Semiconductor Bonding Technologies Inc.

Philip R Osborn

Belgacem Haba

Ilyas Mohammed

Hiroaki Sato

Teck-Gyu Kang

Ellis Chau

Wei-Shun Wang

Norihito Masuda

Kazuo Sakuma

Kiyoaki Hashimoto

Tomoyuki Kikuchi

Kurosawa Inetaro

Wael Zohni

Philip Damberg

Masud Beroz

David A Gibson

Michael Warner

Jae M Park

Young-Gon Kim

Mihalis Michael

Fion Tan

Jennifer Fosberry

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

Package-on-package assembly with wire bonds to encapsulation surface

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts.

Microelectronic packages having cavities for receiving microelectronic elements

First and second bond elements, e.g., wire bonds, electrically connect a chip contact with one or more substrate contacts of a substrate, and can be arranged so that the second bond element is joined to the first bond element at each end and so that the second bond element does not touch the chip contact or one or more substrate contacts. A third bond element can be joined to ends of the first and second bond elements. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact.

Microelectronic assembly with joined bond elements having lowered inductance

A microelectronic assembly includes a substrate having a first surface and a second surface remote from the first surface. A microelectronic element overlies the first surface and first electrically conductive elements are exposed at one of the first surface and the second surface. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer extends from the first surface and fills spaces between the wire bonds such that the wire bonds are separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.

A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact.

Growing community of inventors

San Jose, CA, United States of America

Philip R Osborn