Cypress Semiconductor Corporation

Philip M Daniell

Grahame K Reynolds

The present invention discloses a method and system of generating and delivering a high voltage signal without latch-up hazards and without incurring a voltage drop due to the threshold of the switching element. The utilization of NMOS elements when switching a high voltage signal may remove latch-up hazards. Switching of the high voltage signal may be accomplished without incurring a voltage drop in the signal. With multiple transistors, switching of a high voltage signal in accordance with the present invention may provide an output driven to a destination circuit on each phase wherein clock cycles may be overlapping and non-overlapping.

High voltage switch with no latch-up hazards

An output buffer is provided in which the output impedance of the buffer is set relatively low during an initial portion of an output transition. Subsequently, near the end of the output transition, the output impedance of the buffer is increased to more closely follow the characteristic impedance of a transmission line driven by the buffer. The output impedance is automatically changed when the buffer output voltage crosses a predetermined threshold. The output buffer includes a voltage threshold detection circuit comprising a diode and a transistor, the diode being coupled to the gate of the transistor. When a voltage level of a signal applied to one of the diode and the transistor crosses a predetermined threshold, a switch state of the diode and/or transistor changes to thereby change an output of the voltage detection circuit and trigger the change of output impedance of the output buffer in a reliable and consistent manner.

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Newbury, United Kingdom

Philip M Daniell