Motorola Corporation

Freescale Semiconductor,inc.

Philip J Tobin

Bich-Yen Nguyen

Hsing-Huang Tseng

Rama I Hegde

David Gilmer

Olubunmi O Adetutu

Bikas Maiti

Srikanth Balaji Samavedam

Christopher C Hobbs

David L O'Meara

Young Limb

Victor S Wang

Fabio Pintchovski

Marius K Orlowski

Chun-Li Liu

James D Hayden

William James Taylor, Jr

James Kenyon Schaeffer, Iii

Dina H Triyoso

J B Price

Vida Ilderem

Hsing H Tseng

Laureen H Parker

Christian A Seelbach

Thomas F McNelly

David G Kolar

Lisa K Garling

Ting Chen Hsu

Mariam G Sadaka

James R Pfiester

Voon-Yew Thean

Alexander Barr

Ted R White

Shawn George Thomas

Israel A Lesk

Paul T Lin

Keith E Witek

Scott S Roth

Tushar Praful Merchant

Michael P Woo

Dean J Denning

Stephen S Poon

Yeong-Jyh Tom Lii

Faivel S Pintchovski

Shih-Wei Sun

Sergio A Ajuria

Jeffrey L Klein

Alexander A Demkov

Wayne J Ray

Leonard John Borucki

Paul G Tsui

Percy V Gilbert

C Joseph Mogab

Matthew W Stoker

Jonathan C Dahm

Shih W Sun

Larry E Frisa

Mark Victor Raymond

John G Franka

Jack Higman

Jim Hayden

Hoang K Nguyen

Joe Mogab

Jen-Jiang Lee

Gary L Huffman

Darrell Roan

Bich Y Nguyen

Yoshio Okada

Amit Nangia

J Olufemi Olowolafe

Jesus Cuellar

E Petyr Wachholz

Glenn Wissen

A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (), such as HfO, is deposited on a semiconductor substrate. A sacrificial layer (), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area () of the substrate is exposed and gate dielectric over a second (nMOS, for example) area () of the substrate continues to be protected by the sacrificial layer. A first gate conductor material () is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.

Method for fabricating dual-metal gate device

One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities

A semiconductor device has a gate with three conductive layers over a high K gate dielectric. The first layer is substantially oxygen free. The work function is modulated to the desired work function by a second conductive layer in response to subsequent thermal processing. The second layer is a conductive oxygen-bearing metal. With sufficient thickness of the first layer, there is minimal penetration of oxygen from the second layer through the first layer to adversely impact the gate dielectric but sufficient penetration of oxygen to change the work function to a more desirable level. A third layer, which is metallic, is deposited over the second layer. A polysilicon layer is deposited over the third layer. The third layer prevents the polysilicon layer and the oxygen-bearing layer from reacting together.

Method of making metal gate transistors

A method for making a semiconductor device includes providing a first substrate region and a second substrate region, wherein at least a part of the first substrate region has a first conductivity type and at least a part of the second substrate region has a second conductivity type different from the first conductivity type. The method further includes forming a dielectric layer over at least a portion of the first substrate region and at least a portion of the second substrate region. The method further includes forming a metal-containing gate layer over at least a portion of the dielectric layer overlying the first substrate region. The method further includes introducing dopants into at least a portion of the first substrate region through the metal-containing gate layer.

Semiconductor device comprising a transistor having a counter-doped channel region and method for forming the same

Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities and a process for forming the same

A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can include O, and two or more dissimilar metallic elements. In one specific embodiment, two dissimilar elements may have the same single oxidation state and be miscible within each other. In one embodiment, the dielectric layer can include an alloy of (HfO)(ZrO), wherein x is between 0 and 1. Each of Hf and Zr has a single oxidation state of +4. Other combinations are possible. Improved electrical and physical properties can include better control over grain size, distribution of grain sizes, thickness of the layer across a substrate, improved carrier mobility, threshold voltage stability, or any combination thereof.

Electronic device including dielectric layer, and a process for forming the electronic device

A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.

Method of manufacturing SOI template layer

A method for forming at least a portion of a semiconductor device includes providing a semiconductor substrate, flowing a first precursor gas over the substrate to form a first metal-containing layer overlying the semiconductor substrate, and after completing said step of flowing the first precursor gas, flowing a first deuterium-containing purging gas over the first metal-containing layer to incorporate deuterium into the first metal-containing layer and to also purge the first precursor gas. The method may further include flowing a second precursor gas over the first metal-containing layer to react with the first metal-containing layer to form a metal compound-containing layer, and flowing a second deuterium-containing purging gas over the metal compound-containing layer to incorporate deuterium into the metal compound-containing layer and to also purge the second precursor gas.

Method for forming a layer using a purging gas in a semiconductor process

A first gate () and a second gate () are preferably PMOS and NMOS transistors, respectively, formed in an n-type well () and a p-type well (). In a preferred embodiment first gate () includes a first metal layer () of titanium nitride on a gate dielectric (), a second metal layer () of tantalum silicon nitride and a silicon containing layer () of polysilicon. Second gate () includes second metal layer () of a tantalum silicon nitride layer on the gate dielectric () and a silicon containing layer () of polysilicon. First spacers () are formed adjacent the sidewalls of the gates to protect the metals from chemistries used to remove photoresist masks during implant steps. Since the chemistries used are selective to polysilicon, the spacers () need not protect the polysilicon capping layers, thereby increasing the process margin of the spacer etch process. The polysilicon cap also facilitates silicidation of the gates.

Capped dual metal gate transistors for CMOS process and method for making the same

A metal oxide, utilized as a gate dielectric, is removed using a combination of gaseous HCl (HCl), heat, and an absence of rf. The metal oxide, which is preferably hafnium oxide, is effectively removed in the areas not under the gate electrode. The use of HCl results in the interfacial oxide that underlies the metal oxide not being removed. The interfacial is removed to eliminate the metal and is replaced by another interfacial oxide layer. The subsequent implant steps are thus through just an interfacial oxide and not through a metal oxide. Thus, the problems associated with implanting through a metal oxide are avoided.

Selective metal oxide removal performed in a reaction chamber in the absence of RF activation

A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

Transistor with layered high-K gate dielectric and method therefor

A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate dielectric layer is then chemically reduced to a metal or a metal hydride. The metal or metal hydride is then removed with a conventional wet etch or wet/dry etch combination. The metal oxide layer may include a metal element such as zirconium, tantalum, hafnium, titanium, or lanthanum and may further include an additional element such as silicon or nitrogen. Reducing the metal oxide layer may includes annealing the metal oxide gate dielectric layer in an ambient with an oxygen partial pressure that is less than a critical limit for oxygen desorption at a given temperature. In another embodiment, reducing the metal oxide gate dielectric layer may include annealing the metal oxide layer while supplying a hydrogen-containing precursor such as silane, ammonia, germane, hydrogen, and hydrazine to the metal oxide gate dielectric layer. The gate electrode may comprise a gate electrode stack that includes a titanium nitride layer over the metal oxide gate dielectric layer and a silicon-containing capping layer over the titanium nitride layer.

Selective removal of a metal oxide dielectric

A semiconductor device and a process for forming the device includes a conductor that overlies an insulating layer. In one embodiment, the conductor includes a first conductive portion, a second conductive portion, and a third conductive portion. The second conductive portion lies between the first and third conductive portions. The first conductive portion includes a first element, and the third conductive portion includes a metal and silicon without a significant amount of the first element. In another embodiment, the conductor is a gate electrode or a capacitor electrode. The conductor includes a first conductive portion, a second conductive portion, a third conductive portion, and a fourth conductive portion. The second conductive portion lies between the first and third conductive portions and has a different composition compared to the first, third, and fourth conductive portion. The third conductive portion lies between the second and fourth conductive portions and has a different composition compared to the first and fourth conductive portions.

Semiconductor device and a process for forming the same

A finished structure ( ) includes a semiconductive region ( ), a first oxide layer ( ), a second oxide layer ( ), and a conductive layer ( ). The first oxide layer ( ) lies between the semiconductive region ( ) and the second oxide layer ( ); and the second oxide layer ( ) lies between the first oxide layer ( ) and the conductive layer ( ). The first oxide layer ( ) includes at least a portion that is amorphous or includes a first element, a second element, and a third element. In the latter, the first element is a metallic element, and each of the first, second, and third elements are different from each other. A process for forming a structure ( ) includes forming a first layer ( ) near a semiconductive region ( ), forming a second layer ( ) after forming the first layer ( ), and forming a third layer ( ) after forming the second layer ( ). The first oxide layer ( ) includes a metallic element and oxygen. The third layer ( ) is a non-insulating layer.

Process for forming a structure

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Austin, TX, United States of America

Philip J Tobin