Intel Corporation

Philip E Freiberger

Ragupathy V Giridhar

Farhad K Moghadam

Leopoldo D Yau

Yi-Ching Lin

Brett E Huff

George E Sery

Brian A Kaiser

Cheng-Sheng Pan

A method of forming a device and the device itself that utilizes a high density plasma-enhanced TEOS-based intermetal dielectric is disclosed. The high density is accomplished though the use of higher RF power and higher oxygen flow rate so that the TEOS is more completely oxidized. The higher density intermetal dielectric absorbs water from air slower than a standard intermetal dielectric film. This lower water absorbance reduces the amount of water in the device and reduces hot electron induced device degradation.

High density TEOS-based film for intermetal dielectrics

A method of precleaning a TEOS oxide layer of a semiconductor device formed by a dep-etch process in order to promote photoresist adhesion to the TEOS oxide layer. The method comprises exposing the TEOS oxide layer to a solution comprising: NH.sub.4 F, buffered HF, and ethylene glycol.

TEOS intermetal dielectric preclean for VIA formation

A method of forming a device having an intermetal dielectric film which is formed and annealed to prevent a significant quantity of ambient moisture from being absorbed by the intermetal dielectric film prior to passivation layer deposition is disclosed. An intermetal dielectric layer is formed over a substrate having a interconnection layer. A second interconnect layer is formed over the IMD layer. The substrate with the intermetal dielectric is annealed anytime between IMD formation and passivation layer deposition to produce a film that does not absorb a significant quantity of ambient moisture, and therefore, longer queue times can be utilized between the anneal and subsequent processing. The present invention reduces the amount of water in the device which reduces hot electron induced device degradation.

Anneal to decrease moisture absorbance of intermetal dielectrics

A method and a device formed by the method of forming a composite dielectric structure between the floating polysilicon electrode and the control electrode of an EPROM-type device is disclosed. The dielectic is characterized by a thin (0-80 angstroms) thermally-grown or CVD bottom oxide layer covered by a relatively thin (&lt;200 angstroms) silicon nitride layer. The top layer comprises a CVD oxide deposited in a thickness up to 150 angstroms. The capacitively measured effective thickness of the complete structure is about 200 .ANG. or less. The top layer CVD oxide has a thickness greater than the bottom oxide layer and greater than or equal to that of the silicon nitride layer and may also extend beyond the EPROM cell to form at least a part of the peripheral transistor dielectric.

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Santa Clara, CA, United States of America

Philip E Freiberger