Adeia Semiconductor Bonding Technologies Inc.

Adeia Semiconductor Technologies LLC

Invensas LLC

Philip Damberg

Belgacem Haba

Ellis Chau

Wei-Shun Wang

Reynaldo Co

Se Young Yang

Roseann Alatorre

Ilyas Mohammed

Hiroaki Sato

Norihito Masuda

Yoshikuni Nakadaira

Kazuo Sakuma

Kiyoaki Hashimoto

Teck-Gyu Kang

Philip R Osborn

Wael Zohni

Richard Dewitt Crisp

Michael Warner

David Bazeley Tuckerman

David A Gibson

Young-Gon Kim

John B Riley, Iii

Zhijun Zhao

Cyprian Emeka Uzoh

Joseph Charles Fjelstad

Charles Gerard Woychik

Craig S Mitchell

Terrence Caskey

Kenneth Allen Honer

Vernon Solberg

Nicholas J Colella

Yukio Hashimoto

Jim Behlen

Rene Kunz

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Package-on-package assembly with wire bond vias

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Semiconductor chip assembly and method for making same

An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.

Substrate and assembly thereof with dielectric removal for increased post height

The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and electrically connecting redistribution contacts on the microelectronic unit and terminals on the substrate with a conductive matrix material extending within at least one opening extending through the substrate.

Method for manufacturing a fan-out WLP with package

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

Impedence controlled packages with metal sheet or 2-layer RDL

A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25&#xb0; and 90&#xb0; relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.

A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential.

Impedance controlled packages with metal sheet or 2-layer rdl

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Cupertino, CA, United States of America

Philip Damberg