Hughes Aircraft Company

Raytheon Company

He Holdings, Inc.

Philip A Trask

Vincent A Pillai

Gabriel G Bakhit

Robert S Miles

George Averkiou

Thomas J Gierhart

Gary B Warren

Kirk R Osborne

Kathryn J Berg

Phase mask laser machining procedures for fabricating high density fine pattern feature electrical interconnection structures. Conductor patterns are fabricated using a phase mask laser patterned dielectric layer as a conductor wet etch masking layer, or by subtractively removing metal using holographic phase mask laser micromachining. In accordance with the present invention, a substrate is provided, a first layer of dielectric material is formed on the substrate, a metal layer is formed on the first layer of dielectric material, and a second layer of dielectric material is then formed on the metal layer. A phase mask is disposed above the second layer of dielectric material that has a predefined phase pattern therein defining a metal conductor pattern that corresponds to an interconnect structure. The second layer of dielectric material is then processed using the phase mask to form the interconnect structure. In a first procedure, the second layer of dielectric material is irradiated through the phase mask using laser energy to remove portions of the second layer of dielectric material and expose the metal layer to define the metal conductor pattern and to provide a dielectric etch mask. Then, the exposed metal layer is wet etched using the dielectric etch mask to form the interconnect structure. A second procedure provides for irradiating the second layer of dielectric material with laser energy through the phase mask to remove portions of the second layer of dielectric material to define a metal conductor pattern. Then, a second metal layer is electrolessly plated, or chemical vapor deposited, in the metal conductor pattern on the exposed surface of the second layer of dielectric material to form the interconnect structure. In a third procedure, the first layer of dielectric material is formed on the substrate, the metal layer is formed thereon, and the phase mask is disposed above the metal layer. The conductor pattern is then directly etched in the metal layer using a laser and the phase mask.

Phase mask laser fabrication of fine pattern electronic interconnect

Methods of producing a chip scale package that enables any chip with peripheral bond pads to be converted to an area array chip scale package suitable for chip on board assembly. The present invention produces the equivalent of a flip chip die when a chip supplier does not provide one. Processing is performed that provides thin film metal interconnections between the chip bond pads and area array bond pads on the bottom of the package. High reliability thin film metal interconnections are thus provided that connect the bond pads of the chip to the area array bond pads to permit external connection to the chip.

Methods of fabricating an HDMI decal chip scale package

Methods of forming two-sided high density multilayer interconnect (HDMI) structures on a relatively large carrier and subsequently releasing and removing one or more structures to provide useable flexible interconnects or decals. In general, a carrier is provided and a release layer is formed on the carrier. Flexible high density multilayer interconnect structures are fabricated on the release layer. The release layer is processed to release and remove one or more flexible HDMI structures from the carrier. The carrier may be an ultraviolet transparent substrate, such as quartz, for example, and the release layer may be a polyimide layer. The HDMI structures are released by irradiating the release layer through the transparent carrier using ultraviolet radiation from an ultraviolet radiation source. Alternatively, a silicon carrier may be used that has a metal or silicon dioxide release layer formed thereon. The HDMI structures are released from the metal or silicon dioxide release layer by using wet etching procedures.

Methods of forming two-sided HDMI interconnect structures

A method of patterning a metallized substrate using a thin partially cured etch block layer. In accordance with the method, a substrate is provided and a layer of metal, such as aluminum, is deposited on the substrate. A thin layer of organic dielectric material, such as polyimide, is deposited over the layer of metal. The thin layer of organic dielectric material is deposited to a thickness on the order one micron, for example, which is thin enough to have etch resistance when acting as an etch block layer for subsequent wet etch patterning of the layer of metal, and thick enough to have no pinhole defects. The deposited thin organic dielectric layer is then partially cured. The underlying layer of metal is then patterned and wet etched using the partially cured thin organic dielectric material as the blocking layer. An additional thick layer of organic dielectric material is then deposited or coated over the patterned layer of metal and partially cured organic dielectric layer. The partially cured organic dielectric layer and the additional thick organic dielectric material are then simultaneously full cured. Upon curing, the partially cured organic dielectric layer conforms to the etched underlying layer of metal.

Method of fabricating metallized substrates using an organic etch block

An electrical interconnection substrate (20) is prepared to receive both wire bonded and soldered connections (60,64,66) by forming a dielectric solder mask (30) over the substrate (20), with openings (36) in the mask (30) to expose the contact pads (22) for which soldered connections are desired. The substrate (20) is exposed to a molten solder alloy (44) in a wave soldering process that dissolves the wire bonding material (28) (preferably gold) from the exposed pads (22) and deposits solder bonding pads (52) in its place. Excess solder is then removed from the substrate, and openings (54) are formed through the solder mask (30) to expose the wire bond contact pads (22'). The selective dissolving of gold bonding layers (28) and their replacement by solder pads (52) prevents the establishment of brittle gold-solder intermetallics, and the deposited solder (52) requires no further heat treatment for correct alloy formation.

Electrical interconnection substrate with both wire bond and solder

A via (26) is formed through a dielectric layer (8) separating two conductive layers (16,28) by establishing a laterally erodible mask (18) over the dielectric (8), with a window (24) over the desired via location. The mask (18) and exposed dielectric material (8) are eroded simultaneously, preferably by reactive ion etching, producing a via (26) through the dielectric (8) which expands laterally as vertical erosion proceeds. The erosion conditions, the materials for the mask (18) and dielectric (8), and the initial window (24) taper are selected so that the final via (26) is tapered at an angle of less than about 45.degree. to the lower metal layer (6), and preferably about 30.degree.-45.degree., to enable a generally uniform width for the upper metallization (28) in the via (26). A non-erodible mask (10) is established over the dielectric layer (8) lateral to the via (26) during fabrication to prevent the propagation of pinhole defects from the erodible mask (18) into the dielectric (8), and is normally removed prior to completing the structure.

Growing community of inventors

Laguna Hills, CA, United States of America

Philip A Trask