Infineon Technologies Ag

Infineon Technologies Austria Ag

Imbera Electronics Oy

Ge Embedded Electronics Oy

Imberatek, LLC

Infineon Technologies Americas Corp.

Petteri Palm

Risto Tuominen

Antti Iihola

Thorsten Scharf

Robert Fehler

Eung San Cho

Josef Hoeglauer

Sergey Yuferev

Frank Daeche

Angela Kessler

Tomasz Naeve

Xaver Schloegel

Maciej Wojnowski

Andrew Neil Sawle

Ralf Wombacher

Zeeshan Umar

Ralf Otremba

Josef Maerz

Tuomas Waris

Edward Fuergut

Gerhard Noebauer

Markus Dinkel

Holger Torwesten

Liu Chen

Elvir Kahrimanovic

Fabian Schnoy

Martin Benisek

Antti Lihola

Mahadi-Ul Hassan

Thomas Gebhard

Joachim Mahler

Ivan Nikitin

Alexander Heinrich

Martin Gruber

Danny Clavette

Frank Pueschner

Irmgard Escher-Poeppel

Peter Stampka

Martin Henning Vielemeyer

Andreas Riegler

Chee Yang Ng

Bernd Schmoelzer

Wae Chet Yong

Josef Gruber

Wolfgang Scholz

Theng Chao Long

Juergen Hoelzl

Martin Buchsbaum

Manfred Schindler

Juan Sanchez

Timo Jokela

Ulrich Froehler

Eslam Abdelhamid

Mark Thomas

Boris Plikat

Arni Kujala

Urban Medic

Tobias Simbeck

Paul Armand Asentista Calo

Milad Mostofizadeh

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

Device including semiconductor chips and method for producing such device

An electronic device is disclosed. In one example, the electronic device comprises a carrier board, a metal inlay having a cavity and being arranged in the carrier board. At least one electronic component is arranged at least partially in the cavity and embedded in the carrier board. Electric contacts are located at a castellated edge of the carrier board.

Electronic device with castellated board

A pre-packaged chip includes a chip having at least one electrical top contact at a top side of the chip and at least one electrical bottom contact at a bottom side, a first laminate layer on the top side, a second laminate layer on the bottom side, the first laminate layer and the second laminate layer being laminated together to sandwich the chip therebetween, a first metal layer on the first laminate layer and electrically contacted to the at least one electrical top contact via at least one top contact hole through the first laminate layer, and a second metal layer on the second laminate layer and electrically contacted to the at least one electrical bottom contact via at least one bottom contact hole through the second laminate layer. The pre-packaged chip is free from any contact hole extending from the first metal layer to the second metal layer.

Pre-packaged chip, method of manufacturing a pre-packaged chip, semiconductor package and method of manufacturing a semiconductor package

A printed circuit board and method of manufacturing a printed circuit board are disclosed. In one example, the method comprises embedding an electronic component in a laminate, and protecting the electronic component against electrostatic discharge during at least part of the manufacturing process by an electrically conductive electrostatic discharge protection structure integrated in the laminate and connected to the electronic component.

Electrostatic discharge protection of electronic component embedded in laminate of printed circuit board

A semiconductor device is disclosed. In one example, the semiconductor device includes a semiconductor chip including a first chip contact pad on a first chip main surface. The semiconductor device further includes a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface. An electrical through connection is electrically coupled to the first electrically conductive layer and to a second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping.

Semiconductor devices including parallel electrically conductive layers

An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate

A die package and method is disclosed. In one example, the die package includes a die having a first die contact on a first side and a second die contact on a second side opposite the first side, and insulating material laterally adjacent to the die. A metal structure substantially directly contacts the surface of the second die contact, wherein the metal structure is made of the same material as the second die contact. A first pad contact on the first side of the die electrically contacts the first die contact, and a second pad contact on the first side of the die electrically contacts the second die contact via the metal structure. The insulating material electrically insulates the metal structure from the first die contact.

Die package and method of forming a die package

In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer and having a first contact pad at a first surface of the semiconductor device. An outer contact pad is positioned on a lower surface of the insulating layer. A vertical redistribution structure electrically couples the first contact pad to the outer contact pad. The first contact pad has a plurality of first via sites. A first subset of the first via sites is occupied by first vias and a second subset of the first via sites remains unoccupied and forms a first via-free zone, such that the first vias are non-uniformly distributed over the first contact pad.

Semiconductor package with non-uniformly distributed vias

A package and method of manufacturing a package is disclosed. In one example, a package which comprises a first transistor chip having a first source pad and a second transistor chip having a second source pad and being stacked with the first transistor chip at an interface area. The first source pad and the second source pad are coupled at the interface area.

Stacked transistor chip package with source coupling

A semiconductor device module includes a package carrier having an opening, wherein in the opening there is disposed a semiconductor package including a semiconductor die, an encapsulant, and first vertical contacts, wherein the encapsulant at least partially covers the semiconductor die, and the first vertical contacts are connected to the semiconductor die and extend at least partially through the encapsulant, and a first outer metallic contact layer electrically connected to the first vertical contacts.

Semiconductor device module having vertical metallic contacts and a method for fabricating the same

A die package is provided. The die package may include a laminated carrier including at least one recess, a first die having a frontside, a backside, a frontside metallization on the frontside and a backside metallization on the backside, wherein the first die is arranged in the at least one recess, a first encapsulating material partially encapsulating the first die, by covering at least the frontside metallization or the backside metallization, and an adhesion promoter material between the metallization covered by the first encapsulation material and the first encapsulation material and in direct physical contact with the first encapsulation material and the metallization covered by the first encapsulation material.

Die package and method of manufacturing a die package

A semiconductor package includes: an electrically insulating core and an electrically conductive first via extending through a periphery region of the core, the core having glass fibres interwoven with epoxy material and one or more regions where the glass fibres are exposed from the epoxy material; a power semiconductor die embedded in an opening in the core and having a first load terminal bond pad which faces a same direction as a first side of the core, a second load terminal bond pad which faces a same direction as a second side of the core, and a control terminal bond pad; a resin that encases the power semiconductor die; a first contact pad plated on the first via at the second side of the core; and a second contact pad plated on the first load terminal bond pad of the power semiconductor die at the first side of the core.

Semiconductor package having an electrically insulating core with exposed glass fibres

A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area.

Semiconductor module having a multi-branch switch node connector

A power semiconductor system includes: a power stage module having one or more power transistor dies attached to or embedded in a first printed circuit board; and an inductor module attached to the power stage module and having an inductor electrically connected to an output node of the power stage module. The inductor includes windings patterned into a second printed circuit board of the inductor module.

Power semiconductor system having an inductor module attached to a power stage module

Growing community of inventors

Wuppertal, Germany

Petteri Palm